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PDF DM9163 Data sheet ( Hoja de datos )
| Número de pieza | DM9163 | |
| Descripción | 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver | |
| Fabricantes | DAVICOM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DM9163 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DM9163
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
DAVICOM Semiconductor, Inc.
DM9163
10/100 Mbps Fast Ethernet Physical Layer Single
Chip Transceiver
DATA SHEET
Doc No: DM9163-16-MCO-DS-P01
August 20, 2014
Version: DM9163-16-MCO-DS-P01
August 20, 2014
1
1 page  
DM9163
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
2 Features
l Fully complies with IEEE 802.3 / IEEE 802.3u 10Base-TX/ 100Base-TX, ANSI X3T12
TP-PMD1995 standards
l Support HP MDI/MDI-X auto crossover function (HP Auto-MDIX)
l Support Auto-Negotiation function, compliant with IEEE 802.3u
l Fully integrated Physical layer transceiver On-chip filtering with direct interface to
magnetic transformer
l Selectable repeater or node mode
l Selectable MII or RMII (Reduced MII) mode for 100Base-TX and 10Base-TX
l Selectable MII or GPSI (7-Wired) mode for 10Base-TX
l Selectable Full-Duplex or Half-Duplex operation
l MII management interface with mask-able interrupt output capability
l Provide Loopback mode for easy system diagnostics
l LED status outputs indicate Link/ Activity, Speed10/100 and Full-Duplex/Collision
l Support Dual-LED optional control
l Support 50MHz clock output in RMII mode
l Single low power Supply of 3.3V with an advanced CMOS technology
l Support 3.3V transformer central tap
l Very Low Power consumption modes
n Power Reduced mode (cable detection)
n Power Down mode
l Compatible with 3.3V and 5.0V tolerant I/Os
l Support BIST function
l 48-pin LQFP
Doc No: DM9163-16-MCO-DS-P01
August 20, 2014
5
5 Page 
DM9163
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
5.5 Bias and Clock
Pin No.
Pin Name
43,42
XT1,XT2
I/O Description
I/O Reference Clock Input
When in Normal MII mode or
when in Reduced MII mode and pin TXCLK is latched high at
the end of reset:
A 25MHz crystal or oscillator as DM9163 reference clock is
used. If the crystal is used, it is connected across pins XT1 and
XT2. If the oscillator is used,
it can either connect to pin XT1 (left pin XT2 unconnected) or
to pin XT2 (left pin XT1 unconnected).
When in Reduced MII mode and pin TXCLK is latched low at
the end of reset:
A 50MHz oscillator is used, and it can either connect to pin
XT1 (left pin XT2 unconnected) or to pin XT2 (left pin XT1
unconnected).
47
BGRESG
P Band gap Ground
48
BGRES
O Band gap Voltage Reference Resistor 6.98K ohm +/- 1%
5.6 Power
Pin No.
1,2,9
5
6
15,33,44
23,30
41
46
Pin Name
AVDD
AGND
AGND
DGND
DVDD33
VDD33
AGND
I/O Description
P Analog 1.8V Regulator Power output
P Analog Receive Ground
P Analog Transmit Ground
P Digital Ground
P Digital Power
P Digital Power for Crystal
P Analog Substrate Ground
5.7 Table (Media Type Selection)
OP2
OP1
OP0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Function
Dual Speed 100/10 HDX
Reserved
Reserved
Manually Select 10TX HDX
Manually Select 10TX FDX
Manually Select 100TX HDX
Manually Select 100TX FDX
Auto-Negotiation Enables All Capabilities
Doc No: DM9163-16-MCO-DS-P01
August 20, 2014
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DM9163.PDF ] | |
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