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PDF BD8139AEFV Data sheet ( Hoja de datos )
| Número de pieza | BD8139AEFV | |
| Descripción | High-precision Gamma Correction IC | |
| Fabricantes | ROHM Semiconductor | |
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Power Supply IC Series for TFT-LCD Panels
High-precision
Gamma Correction ICs with built-in DAC
BD8132FV, BD8139AEFV
No.09035EBT02
●Description
These gamma correction voltage generation ICs feature built-in DACs and provide a single-chip solution with setting control
via serial communications, a high-precision 10-bit DAC, an output amp (18-channel or 10-channel), and Vcom.
●Features
1) Single-chip design means fewer components
2) Built-in 10 bit DAC (18ch: BD8132FV, 10ch: BD8139AEFV)
3) Built-in DAC output amp
4) Built-in Vcom amp
5) Built-in auto-read function
6) 3-line serial interface (BD8132FV) or 2-wire serial (BD8139AEFV)
7) Thermal shutdown circuit
8) SSOP-B40 package (BD8132FV) / HTSSOP-B40 package (BD8139AEFV)
●Applications
These ICs can be used with TFT LCD panels used by large-screen and high-definition LCD TVs.
●Absolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Limit
Power supply voltage 1
DVcc
7
Power supply voltage 2
Vcc 20
REFIN voltage
REF
20
Amp output current capacity
Io 50*1
Junction temperature
Tjmax
150
Power dissipation
BD8132FV
BD8139AEFV
Pd
1125*2
1600*3
Operating temperature range
Topr -30 to +85
Storage temperature range
Tstg -55 to +150
*1 Must not exceed Pd.
*2 Reduced by 9.0 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm).
*3 Reduced by 12.8 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm).
Unit
V
V
V
mA
℃
mW
℃
℃
●Recommended Operating Ranges
Parameter
Power supply voltage 1
Power supply voltage 2
REFIN voltage
Amp output current capacity
Serial clock frequency (BD8132FV)
2 wire serial frequency (BD8139AEFV)
OSC frequency (BD8132FV)
OSC frequency (BD8139AEFV)
Symbol
DVcc
Vcc
REF
Io
fCLK
fCLK
fosc
fosc
Limit
Min. Max.
2.3 4.0
6 18
6 18
— 40
—5
— 400
10 200
— 400
Unit
V
V
V
mA
MHZ
kHz
kHz
kHz
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
1/20
2009.07 - Rev.B
1 page  
BD8132FV, BD8139AEFV
●Reference Data
(Unless otherwise specified, Ta = 25℃, BD8132FV and BD8139AEFV)
80
60
40
20
0
100
100
80
60
Phase
40
20
0
Gain
-20
-40
-60
-80
-100
1 10K 100K 1M 10M
FREQUENCY : f [Hz]
Fig. 10 Open Loop Waveform
1000
100
10
1
0.1
0.01
0.0001
0.001 0.01
0.1
1
CT CAPACITOR : CT[μF]
10
Fig. 11 Power-on Reset Time
Technical Note
100
80
60
40
20
0
-40 -20 0 20 40 60 80 100
AMBIENT TEMPERATURE : Ta[℃]
Fig. 12 Power-on Reset Time
vs Temperature
VCC=15V
VI=4V
RL=100kΩ
CL=100pF
TA=25℃
6
4
2
10 0
8
6
4
2
0
0 5 10 15 20 25 30 35 40 45 50
TIME [usec]
Fig. 13 Slew Rate Waveform
(High-Amplitude)
VCC=15V
VI=40mV
RL=100kΩ
CL=100pF
TA=25℃
2.55
2.50
5.10
2.45
5.05
5.00
4.95
4.90
0 5 10 15 20 25 30 35 40 45 50
TIME [usec]
Fig. 14 Slew Rate Waveform
(Small Signal)
VCC=15V
VI=5V
CS=100pF
RS=100Ω
CL=100pF
RL=1kΩ
tT=0.1us
TA=25℃
10.2
+20mA
-20mA
10.1
9.9
9.80 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME [usec]
Fig. 15 Load Response Waveform
(RL = 1 k Pull-up)
VCC=15V
VI=5V
CS=100pF
RS=100Ω
CL=100pF
RL=1kΩ
tT=0.1us
TA=25℃
10.2
10.1
9.9
9.8
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME [usec]
Fig. 16 Load Response Waveform
(RL = 1 k Pull-down)
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
200 400 600 800 1000
step
Fig. 17 Integral Linearity Error
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
200 400 600 800 1000
step
Fig. 18 Differential Linearity Error
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
5/20
2009.07 - Rev.B
5 Page 
BD8132FV, BD8139AEFV
Technical Note
●Timing standard values
Parameter
Latch setup time
SDIN setup time
RW setup time
MEMDI setup time
Clock high time
Clock low time
Latch hold time
RW hold time
LATCH high time
RW high time
MEMDO delay time
CS delay time
Symbol
tLC
tSC
tRC
tDIC
tWH
tWL
tCL
tCR
tLA
tRW
tCDO
tCCS
Min.
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.6
0.6
—
—
Limit
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
—
—
0.1
0.1
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
●Gamma correction output setting (BD8132FV and BD8139AEFV)
Equation (1) describes the relationship between the gamma correction output voltage (V0 to VH) and the DAC setting.
Output voltage (V0 to VH) = [(DAC setting + 1) / 1,024] (REFIN / 2) 2
(1)
The Vcom voltage can be set by attaching resistor R1 between the Vcom and FB pins and resistor R2 between the FB and
GND pins.Equation (2) describes the relationship between the Vcom voltage and the DAC setting when using these resistors.
Output voltage (Vcom) = [(DAC setting + 1) / 1,024] (REFIN / 2) (R1 + R2) / R2
(2)
DAC Vcom
FB
R2
R1
Fig. 27 Vcom Voltage Setting Circuit Diagram
●Power supply sequence
Activate the digital power supply DVCC before the VCC power supply to prevent IC malfunctions due to undefined logic in the digital
circuit. Input serial data after canceling the power-on reset. When turning off the IC's power supplies, turn off VCC and then DVCC.
VCC
REFIN
DVCC
LATCH
tDS
・・・
・・・
・・・
tVcc
tVR
・・・
・・・
・・・
・・・
tSV
・・・
tVD
tRV
CLK
SDIN
・・・
・・・
・・・
・・・
Fig. 28 Power Supply Sequence Diagram
●Power supply sequence standard values
Parameter
Symbol
Min.
Limit
Typ.
Max.
Unit
Serial input timing
tDS 100 — —
µs
VCC activation timing
tSV 0 10 —
µs
REFIN activation timing
tVR 0 10 —
µs
REFIN off timing
tRV 0 10 —
µs
Power supply off timing
tVD 0 10 —
µs
VCC startup timing
tVCC
1
——
ms
Condition
Cct = 1000 pF
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
11/20
2009.07 - Rev.B
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet BD8139AEFV.PDF ] | |
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