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PDF BD7710GWL Data sheet ( Hoja de datos )

Número de pieza BD7710GWL
Descripción 1.5A LED Camera Flash Driver
Fabricantes ROHM Semiconductor 
Logotipo ROHM Semiconductor Logotipo



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No Preview Available ! BD7710GWL Hoja de datos, Descripción, Manual

1.5A LED Camera Flash Driver
with I2C Compatible Interface
BD7710GWL
General Description
The BD7710GWL is 1.5A Flash LED Driver with
Synchronous rectification step up DC/DC converter that
can drive 3LED.
It is possible to set by I2C interface.
With synchronous rectification (no external schottky
barrier diode required) and small package, they can
save mount space.
Features
1) Synchronous rectification step-up DC/DC
converter.(no external S.B.D.)
2) 3 channel current driver (maximum total 1.6A)
3) It is possible to control register by I2C interface
4) Programmable lighting mode
5) Programmable LED current
6) Programmable Battery drop protection
7) Programmable Flash timer
8) Rich safety function
Over Current Protection (OCP)
Over Voltage Protection (OVP)
VOUT Short Protection
LED short/open Protection
UVLO
TSD
Battery drop Protection
LED Temperature Monitoring
Key Specifications
VBAT Input voltage
Operating temperature range
Quiescent Current
LED Current
Switching frequency
2.7V to 5.5V
-40to +85
3.0μA(MAX)
1.6A(MAX)
2MHz(typical)
Packages
UCSP50L2
1.90 ㎜×2.10 ㎜×0.55 (MAX)
Applications
Single/Dual/Triple White LED Flash Supply for
Cell Phones and Smart-Phones
DSC,DVC
Video Lighting for Digital Video Applications
Amusement accessory
Typical Application Circuits
Pin Configuration [Bottom View]
CIN
4.7µF
L
2.2µH
E LED2 LED1 LED3 VBAT
battery
I2C I/F
VBAT
RESETB
SCL
SDA
SW SW
STRB0
STRB1
TX_MASK
NC
PGND GND
TS
VOUT
LED1
LED2
LED3
NC
COUT D PGND PGND STRB1 NC
10µF
C SW SW TX_MASK TS
B
SDA
SCL RESETB STRB0
A NC VOUT GND GND
Figure 1. 1.5A application Block diagram
1 2 34
Figure 2. Pin Configuration
Product structureSilicon monolithic integrated circuit
.www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211114001
This product is not designed protection against radioactive rays
1/36
TSZ02201-0F2F0C200010-1-2
20.May.2013 Rev.003

1 page




BD7710GWL pdf
BD7710GWL
Typical Characteristics (Reference Data)
Y-axis
Quiescent Current
Current Consumption
ILED(100mA)
ILED(400mA)
Efficiency
UVLO
Frequency
Over Voltage Protection (OVP)
VOUT Short Protection
Over Current Protection (OCP)
TS Current source
TS Resistance (Warning temperature)
TS Resistance (Hot temperature)
X-axis
VBAT
VBAT
VBAT
VBAT
VBAT
Temperature
VBAT
VBAT
VBAT
VBAT
Temperature
Temperature
Temperature
Datasheet
Figure-No
Figure5-1
Figure5-2
Figure5-3
Figure5-4
Figure5-5
Figure5-6
Figure5-7
Figure5-8
Figure5-9
Figure5-10
Figure5-11
Figure5-12
Figure5-13
3
2.5
2
1.5
85
25
1
0.5
-40
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VBAT [V]
Figure 5-1. Quiescent Current – VBAT
12
85
11
10
9
8
-40
25
7
6
5
4
3
2
1
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VBAT [V]
Figure 5-2. Current Consumption - VBAT
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
5/36
TSZ02201-0F2F0C200010-1-2
20.May.2013 Rev.003

5 Page





BD7710GWL arduino
BD7710GWL
Datasheet
(8) Timing diagram
SDA
t LOW
t SU;DAT
t HD;STA
t BUF
SCL
t HD;STA
S
t HD;DAT
t HIGH
t SU;STA
Sr
Figure 12. Timing diagram (I2C format)
t SU;STO
P
S
(9) Electrical Characteristics (Unless otherwise specified, Ta=25 oC, VBAT=3.6V)
Parameter
I2C BUS format (F/S-mode)
Standard-mode
Symbol
Min. Typ. Max.
SCL clock frequency
FSCL
0
- 100
LOW period of the SCL clock
tLOW
4.7
-
-
HIGH period of the SCL clock
tHIGH
4.0
-
-
Hold time (repeated) START condition
After this period, the first clock is generated
tHD;STA
4.0
-
-
Set-up time for a repeated START
condition
tSU;STA
4.7
-
-
Data hold time
tHD;DAT
0
- 3.45
Data set-up time
tSU;DAT 250
-
-
Set-up time for STOP condition
Bus free time between a STOP
and START condition
tSU;STO
tBUF
4.0
4.7
-
-
-
-
Fast-mode
Min. Typ. Max.
0 - 400
1.3 -
-
0.6 -
-
0.6 -
-
0.6 -
-
0 - 0.9
100 -
-
0.6 -
-
1.3 -
-
Unit
kHz
μs
μs
μs
μs
μs
ns
μs
μs
Parameter
I2C BUS format (Hs-mode)
SCL (SCLH) clock frequency
Symbol
FSCL
Cb=100pF(max)
Min. Typ. Max.
0 - 3.4
LOW period of the SCL (SCLH) clock
TLOW
160
-
-
HIGH period of the SCL (SCLH) clock
tHIGH
60
-
-
Hold time (repeated) START condition
After this period, the first clock is tHD;STA
generated
160
-
-
Set-up time for a repeated START
condition
tSU;STA
160
-
-
Data hold time
tHD;DAT
0
- 70
Data set-up time
tSU;DAT
10
-
-
Set-up time for STOP condition
tSU;STO
160
-
-
Capacitive load for each bus line
[SDA (SDAH) and SCL (SCLH) lines]
Cb - - 100
(Note) For bus line loads Cb between 100 pF and 400 pF the timing parameters must be linearly interpolated
Cb=400pF
Min. Typ. Max.
0-
320 -
120 -
1.7
-
-
320 -
-
Unit
MHz
ns
ns
ns
320 -
- ns
0 - 150 ns
10 -
- ns
320 -
- ns
- - 400 pF
www.rohm.com
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ2211115001
11/36
TSZ02201-0F2F0C200010-1-2
20.May.2013 Rev.003

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