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PDF 82P33831 Data sheet ( Hoja de datos )

Número de pieza 82P33831
Descripción Synchronization Management Unit
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! 82P33831 Hoja de datos, Descripción, Manual

Synchronization Management Unit for
IEEE 1588 and 10G/40G Synchronous
Ethernet
82P33831
Short Form Datasheet
This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on
the last page.
HIGHLIGHTS
• Synchronization Management Unit (SMU) provides tools to manage
physical layer and packet based synchronous clocks for IEEE 1588 /
PTP Telecom Profile applications
• Supports independent IEEE 1588 and Synchronous Ethernet (SyncE)
timing paths
• Combo mode provides SyncE physical layer frequency support for
IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time Slave
Clocks (T-TSC) per G.8273.2
• Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally Con-
trolled Oscillators (DCOs) for PTP clock synthesis
• DCO frequency resolution is [(77760 / 1638400) * 2^-48] or
~1.686305041e-10 ppm
• DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks
• Two independent Time of Day (ToD) counters/time accumulators, one
associated with each of DPLL1 and DPLL2, can be used to track dif-
ferences between the two time domains and to time-stamp external
events
• DPLL3 performs rate conversions to frequency synchronization inter-
faces or for other general purpose timing applications
• APLL3 is Voltage Controlled Crystal Oscillator (VCXO) based and
generates clocks with jitter <0.3 ps RMS (10 kHz to 20 MHz) for:
10GBASE-R, 10GBASE-W and 40GBASE-R
• APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to
20 MHz) for: 1000BASE-T and 1000BASE-X
• Fractional-N input dividers support a wide range of reference frequen-
cies
• Locks to 1 Pulse Per Second (PPS) references
• DPLLs, APLL1 and APLL2 can be configured from an external
EEPROM after reset
FEATURES
• Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization
interface signals per ITU-T G.703
• Differential reference inputs (IN3 to IN8) accept clock frequencies
between 1 PPS and 650 MHz
• Single ended inputs (IN9 to IN14) accept reference clock frequencies
between 1 PPS and 162.5 MHz
• Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
• Reference monitors qualify/disqualify references depending on activ-
ity, frequency and LOS pins
• Automatic reference selection state machines select the active refer-
ence for each DPLL based on the reference monitors, priority tables,
revertive and non-revertive settings and other programmable settings
• Fractional-N input dividers enable the DPLLs to lock to a wide range
of reference clock frequencies including: 10/100/1000 Ethernet, 10G
Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS fre-
quencies
• Any reference input (IN3 to IN14) can be designated as external sync
pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-
able reference clock input
• FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input and
frequency locked to the associated reference clock input
• DPLL1 and DPLL2 can be configured with bandwidths between 0.09
mHz and 567 Hz
• DPLL1 and DPLL2 lock to input references with frequencies between
1 PPS and 650 MHz
• DPLL3 locks to input references with frequencies between 8 kHz and
650 MHz
• DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous Ether-
net Equipment Clock (EEC), and G.813 for Synchronous Equipment
Clock (SEC); and Telcordia GR-253-CORE for Stratum 3 and SONET
Minimum Clock (SMC)
• DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1
• DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE
1588 clocks
• DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on
OUT9 and OUT10
• APLL1, APLL2 and APLL3 can be connected to DPLL1 or DPLL2
• APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or
SONET/SDH frequencies
• APLL3 generates 10G Ethernet, WAN-PHY and LAN-PHY frequen-
cies
• Any of eight common TCXO/OCXO frequencies can be used for the
System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,
24.576 MHz, 25 MHz or 30.72 MHz
• The I2C slave interface can be used by a host processor to access the
control and status registers
• The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset; APLL3 must be configured
via the I2C slave interface
• DPLL1 or DPLL3 can be connected to an internal composite clock
generator that outputs its 64 kHz synchronization signal on OUT8
• Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
• Differential outputs OUT11 and OUT12 output clocks with frequencies
up to 650 MHz
• Single ended outputs OUT1, OUT2 and OUT7 output clocks with fre-
quencies between 1 PPS and 125 MHz
• Single ended outputs OUT9 and OUT10 output clocks N*8kHz multi-
ples up to 100 MHz
• DPLL1 and DPLL2 support independent programmable delays for
each of IN3 to IN14; the delay for each input is programmable in steps
of 0.61 ns with a range of ~±78 ns
• The input to output phase delay of DPLL1 and DPLL2 is programma-
ble in steps of 0.0745 ps with a total range of ±20 μs
• The clock phase of each of the output dividers for OUT1 (from APLL1)
to OUT7 is individually programmable in steps of ~200 ps with a total
range of +/-180°
• 1149.1 JTAG Boundary Scan
• 144-pin CABGA green package
©2016 Integrated Device Technology, Inc.
1
Revision 6, March 24, 2016

1 page




82P33831 pdf
82P33831 Short Form Datasheet
1 PIN ASSIGNMENT
1 2 3 4 5 6 7 8 9 10 11 12
A OUT5_POS OUT5_NEG OUT6_POS OUT6_NEG VDDAO OUT12_POS VDDAO  OUT11_POS CAP2
SONET/SDH/LO
XTAL2_IN S3 XTAL1_IN
A
B
VSSAO
VDDAO
VDDAO
VSSAO
VSSAO OUT12_NEG VSSAO OUT11_NEG
VSSA
XTAL2_OUT MPU_MODE1/I XTAL1_OUT
2CM_SCL
B
C VDDA
VSSA
VSS
OUT7
I2C_SDA
VDDA
VDDA
IC
CAP1
IC
MPU_MODE0/I MFRSYNC_2
2CM_SDA
K_1PPS
C
D VSSA
VDDA
VSSCOM
VSSD
VDDD
VSSA
VSSA
CAP3
I2C_AD2 I2C_SCL
OUT10
OUT9
D
E OSCI
VSSA
IC
VDDDO
I2C_AD1
VDDD0
VSSDO
VSSA DPLL3_LOCK IN14
IN13
FRSYNC_8K_
1PPS
E
F
TMS
VDDA
VSSA
VSSDO
VSS
VSSD
VDDD
VSSA
VDDA
IN12
IN8_NEG
IN8_POS
F
G TCK
VDDA
IC
VSS VSS VSS
IC
VSS DPLL2_LOCK IN11
IN7_NEG
IN7_POS
G
H
XO_FREQ0/
LOS0
VDDA
VSSA
VSS
VSS
VSS
VSS
VSS DPLL1_LOCK IN10
VSSD
VDDD_1_8 H
J
XO_FREQ1/ XO_FREQ2/
LOS1
LOS2
VSS
VSS
VSS
VSS
VSS
VSS INT_REQ IN9
IN6_NEG
IN6_POS
J
K VDDA
VDDA
TRSTB
VSSAO
OUT2
RSTB
VSSDO
MS_SL
IN2
IN1
IN5_NEG
IN5_POS
K
L VSSA
VSSA
TDI
VDDAO
TDO
IC
VDDDO
OUT1
VSSD
VDDD_1_8 IN4_NEG
IN4_POS
L
M OUT4_POS OUT4_NEG VSSAO
VDDAO OUT3_POS OUT3_NEG VSSDO
VDDDO OUT8_POS OUT8_NEG IN3_NEG
IN3_POS M
1 2 3 4 5 6 7 8 9 10 11 12
Figure 2. Pin Assignment (Top View)
©2016 Integrated Device Technology, Inc.
5
Revision 6, March 24, 2016

5 Page





82P33831 arduino
82P33831 Short Form Datasheet
Figure 4. 144-Pin BAG Package Recommended Land Pattern
©2016 Integrated Device Technology, Inc.
11
Revision 6, March 24, 2016

11 Page







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