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PDF 8T49N4811 Data sheet ( Hoja de datos )
| Número de pieza | 8T49N4811 | |
| Descripción | I2C Programmable Ethernet Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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I2C Programmable Ethernet Clock
Generator
8T49N4811
DATA SHEET
General Description
The 8T49N4811I is a highly flexible FemtoClock® NG
pin-programmable clock generator suitable for networking and
communications applications. It is able to generate five different
output frequencies with multiple copies of each. A fundamental mode
crystal, single-ended, or differential input reference may be used as
the source for the output frequency.
The use of pin-programming to select the input source / frequency,
desired output frequencies and output styles allow a single device to
be used in a wide variety of applications without the need for register
programming.
Selection pins use 3-level options to maximize flexibility while
minimizing package size. Selection is performed by tying a selection
pin high or low or by leaving it floating, eliminating the need for
passive components to drive a desired logic level.
Features
• Fourth generation FemtoClock® NG technology
• Generates multiple copies of 25MHz, 50MHz, 100MHz, 125MHz,
156.25MHz or 312.5MHz
• Typical input frequency is 25MHz, with optional 125MHz and
156.25MHz input support
• Differential outputs are pin programmable for LVDS or LVPECL
• RMS phase jitter at 156.25MHz: <300fs typical
• Power Supply Rejection Ratio better than -50dBc from
10k-1.5MHz at 3.3V power supply
• Full 3.3V and 2.5V Supply Voltages
• -40°C to +85°C ambient operating temperature
• 56-pin VFQFPN, lead-free (RoHS 6) packaging
Block Diagram
2.5V ±5% or 3.3V ±10%
PLL Bypass
SDATA, SCLK
IIC_ADRX_SEL
IN_SEL
XTAL_IN
fIN XTAL_OUT
DIN
nDIN
SLEW_LVCMOS
LVCMOS_CTRL
Qx_CTRL
QB_CTRL [1:0]
INPUT_DIVSEL
DIVSEL_x
100Ω
3
4
/A 0
1
OSC 0
1
fIN APLL
/B 0
1
/C 0
1
/D0
Frequency,
Output Type,
Slew Rate, &
Output Enable
Control
Input Divider
Frequency Select
/D1
Output Enable,Type, & Slew Rate Control
Bank A 1 LVPECL/LVDS
125MHz/156.25MHz/312.5MHz
Bank B 6 LVPECL/LVDS
50MHz/125MHz/156.25MHz
Bank C 2 LVPECL/LVDS
100MHz/125MHz/156.25MHz
Bank D0 1 LVPECL/LVDS
25MHz/125MHz/156.25MHz
Bank D1 1 LVCMOS
25MHz/125MHz
8T49N4811 REVISION A 3/30/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
Function Tables
Table 3A. Input Frequency Select Table
0
1
Float
INPUT_DIVSEL
25MHz
125MHz
156.25MHz
Table 3B. Slew Rate Control Table
0 (default)
1
SLEW_LVCMOS
Normal
Slow
Table 3C. PLL Bypass Table
0 (default)
1
PLL_BYPASS
Normal Operation
PLL Bypassed
Table 3D. I2C Address Selection Table
IIC_ADRX_SEL
0 (default)
1
Address
DC (h)
DE (h)
Table 3E. Bank A Frequency Select Table
DIVSEL_A
0
1
Float
Frequency
156.25MHz
125MHz
312.5MHz
Table 3F. Bank B Frequency Select Table
DIVSEL_B
0
1
Float
Frequency
156.25MHz
125MHz
50MHz
8T49N4811 DATA SHEET
Table 3G. Bank C Frequency Select Table
DIVSEL_C
0
1
Float
Frequency
156.25MHz
125MHz
100MHz
Table 3H. Bank D1 LVCMOS Control Table
LVCMOS_CTRL
0
1
Float
State
High Impedance
125MHz
fIN
Table 3I. Bank D0 QD0 Frequency Select Table
DIVSEL_D0
0
1
Float
Frequency
156.25MHz
125MHz
fIN
Table 3J. Clock Select Function Table
Control Input
IN_SEL
0
1
Float
Clock
Crystal
Selected
De-selected
Selected
(Doubler = ON)
DIN, nDIN
De-selected
Selected
De-selected
Table 3K. Qx_CTRL and QB_CTRL[1:0] Pin Table
Bank Mode Pin
0
1
Float
Bank Mode
LVPECL
LVDS
Selected; Note 1, 2
De-selected
De-selected
Selected; Note 1, 2
High Impedance;
Note 3
High Impedance;
Note 3
NOTE 1: QD_CTRL affects differential outputs ONLY.
NOTE 2: QB_CTRL0 affects outputs QB[0:2]. QB_CTRL1 affects
outputs QB[3:5].
NOTE 3: High impedance mode: 100k pulldown on true output, 100k
pullup on compliment output.
REVISION A 3/30/15
5 I2C PROGRAMMABLE ETHERNET CLOCK GENERATOR
5 Page 
8T49N4811 DATA SHEET
Table 5C. LVCMOS Input DC Characteristics, VDD = VDD_ODS = 3.3V±10% or 2.5V±5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VIH
Input
Except SCLK,
High Voltage SDATA
VDD = 3.3 V ±10%
VDD = 2.5 V ±5%
VIH
Input
High Voltage
SCLK, SDATA
VDD = 3.3 V ±10%
VDD = 2.5 V ±5%
VIL Input Low Voltage
Pullup Inputs
IIH
Input
High Current Pulldown
Inputs
VDD = 3.3 V ±10%
VDD = 2.5 V ±5%
VDD = VIN = VDD MAX
Pullup Inputs
IIL
Input
Low Current Pulldown
Inputs
VDD = VDD MAX, VIN = 0 V
VOH
Output
LVCMOS
High Voltage Outputs
VDD_ODS = 3.3V ±10%; IOH = –12 mA
VDD_ODS = 2.5V± 5%; IOH = –8 mA
VOL
Output
LVCMOS
Low Voltage Outputs
VDD_ODS = 3.3V ±10%; IOL = 12 mA
VDD_ODS = 2.5V± 5%; IOL = 8 mA
2
1.7
2.4
1.8
-0.3
-0.3
-150
-5
2.45
1.8
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
0.8
0.5
5
150
0.5
0.5
NOTE: Core supply voltage cannot be lower than the output supply voltage.
Units
V
V
V
V
V
V
µA
µA
µA
µA
V
V
V
V
Table 5D. Differential Input DC Characteristics, VDD = 3.3V±10% or 2.5V±5%, TA = -40°C to 85°C
Symbol
VPP
VCMR
IIH
IIL
Parameter
Peak to Peak Input Voltage;
NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
Input
High Current; DIN, nDIN
NOTE 3
Input
Low Current; DIN, nDIN
NOTE 3
Test Conditions
nDIN = Open,
VDD = VIN = VDD MAX
DIN = Open,
VDD = VIN = VDD MAX
nDIN = Open,
VDD = VDD MAX, VIN = 0 V
DIN = Open,
VDD = VDD MAX, VIN = 0 V
Minimum
0.15
0.5
Typical
-225
-225
NOTE: Core supply voltage cannot be lower than the output supply voltage.
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as the cross point.
NOTE 3: The differential inputs have internal 100 and biased to VDD–1.3V approximately.
Maximum
1.3
Units
V
VDD - 0.85
V
175 µA
175 µA
µA
µA
REVISION A 3/30/15
11 I2C PROGRAMMABLE ETHERNET CLOCK GENERATOR
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 8T49N4811.PDF ] | |
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