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PDF IDT8T79S818I-08 Data sheet ( Hoja de datos )

Número de pieza IDT8T79S818I-08
Descripción 1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer
Fabricantes Integrated Device Technology 
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1-to-8 Differential to Universal Output
Clock Divider/Fanout Buffer
IDT8T79S818I-08
DATASHEET
General Description
The IDT8T79S818I-08 is a high performance, 1-to-8, differential input
to universal output clock divider and fanout buffer. The device is
designed for frequency-division and signal fanout of high-frequency
clock signals in applications requiring four different output
frequencies generated simultaneously. Each bank of two outputs has
a selectable divider value of ÷1 through ÷6 and ÷8. The
IDT8T79S818I-08 is optimized for 3.3V and 2.5V supply voltages and
a temperature range of -40°C to 85°C. The device is packaged in a
space-saving 32 lead VFQFN package.
Features
Four banks of two low skew outputs
Selectable bank output divider values: ÷1 through ÷6 and ÷8
One differential PCLK, nPCLK input
PCLK, nPCLK input pair can accept the following differential input
levels: LVPECL, LVDS levels
Maximum input frequency: 1.5GHz
LVCMOS control inputs
QXx ÷1 edge aligned to QXx ÷n edge
Individual output divider control via serial interface
Individual output enable/disable control via serial interface
Individual output type control, LVDS or LVPECL, via serial
interface
2.375V to 3.465V supply voltage operation
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
Block Diagram
VCC
VCC 25
VEE 26
nQA1 27
QA1 28
nQA0 29
QA0 30
VCC 31
SDATA 32
IDT8T79S818I-08
32 lead VFQFN
5mm x 5mm x 0.925mm
Pad size 3.15mm x 3.15mm
NL package
Top View
16 VCC
15 VEE
14 QD0
PCLK Pulldown
nPCLK Pullup/Pulldown
VEE VEE
13 nQD0
12 QD1
11 nQD1
10 VCC
PWR_SEL Pulldown
9 PWR_SEL
VEE
Dividers
RST
7
nRST Pullup
OE Pulldown
LE Pulldown
SCLK Pulldown
SDATA Pulldown
VCC
D ivid e r S e le ct,
Output Type and
O utput Enable
logic
VEE VEE VEE VEE
12
10
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
QC0
nQC0
QC1
nQC1
QD0
nQD0
QD1
nQD1
MISO
IDT8T79S818A-08NLGI REVISION A JULY 11, 2013
1
©2013 Integrated Device Technology, Inc.

1 page




IDT8T79S818I-08 pdf
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Serial Interface
Configuration of the IDT8T79S818I-08 is achieved by writing 22
configuration bits over serial interface. All 22 bits have to be written in
sequence.
After writing the 22 configuration bits, the LE pin must remain at high
level for outputs to toggle.
SCLK
SDATA
LE
D22
tSL
tS
D21
tH
MISO
tDELAY
D22
tHI tLO
D3 D2
D21 D3
tSH
D1
t HE
D2 D1
Figure 2. Serial Interface Timing Diagram for Write and Read Access
Table 3D. Timing AC Characteristics
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
tS
tH
tHE
tHI
tLO
tSL
tSH
tDELAY
Data to Clock Setup Time
Data to Clock Hold Time
Clock to LE Hold Time
Clock High Duration
Clock Low Duration
LE to Clock Setup Time
LE to SCLK Setup Time
Clock to MISO Delay Time
10 ns
10 ns
10 ns
25 ns
25 ns
10 ns
10 ns
10 ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
5
©2013 Integrated Device Technology, Inc.

5 Page





IDT8T79S818I-08 arduino
IDT8T79S818I-08 Data Sheet
1-TO-8 DIFFERENTIAL TO UNIVERSAL OUTPUT, CLOCK DIVIDER/FANOUT BUFFER
Parameter Measurement Information
2V
2V
VCC
SCOPE
Qx
VCC
SCOPE
Qx
nQx
VEE
-1.3V ± 0.165V
3.3V LVPECL Output Load Test Circuit
nQx
VEE
-0.5V ± 0.125V
2.5V LVPECL Output Load Test Circuit
VCC
VCC
3.3V LVDS Output Load Test Circuit
VCC
nPCLK
PCLK
VEE
Differential Input Levels
IDT8T79S818A-08NLGI REVISION B JULY 11, 2013
2.5V LVDS Output Load Test Circuit
nPCLK
PCLK
nQXx
QXx
tPD
Propagation Delay
11 ©2013 Integrated Device Technology, Inc.

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