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PDF IDT8T49N524I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T49N524I | |
| Descripción | NG LVPECL/LVDS Dual 4-Output Fractional Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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Programmable FemtoClock® NG LVPECL/LVDS
Dual 4-Output Fractional Clock Generator
IDT8T49N524I
DATA SHEET
General Description
The IDT8T49N524I is an eight output programmable any-rate dual
clock generator with selectable LVDS or LVPECL outputs. Both clock
generators use Fractional Output Dividers to be able to generate out-
put frequencies that are independent of each other and independent
of the input frequency. Output frequencies for both clock generators
are generated from a single crystal or reference clock.
Clock Generator A supports three different factory-programmed
default frequencies that can be selected from using only the FSEL
control pins. Alternatively any desired output frequency can be
programmed over the I2C serial port. The chosen output frequency is
then driven out the QA0 to QA3 outputs.
Clock Generator B supports a single factory-programmed default
frequency. It can also be programmed for any output frequency via
the serial port. The output frequency is driven out the QB0 to QB3
outputs.
Some examples of frequency configurations that can be achieved
are shown in Table 5A. Please consult IDT for programming software
that can be used to determine the required settings for any desired
configuration.
Excellent phase noise performance is achieved with IDT’s fourth
Generation FemtoClock® NG PLL technology, which delivers
sub-0.5ps RMS phase jitter in the integer divide mode.
Features
• Fourth Generation FemtoClock® NG PLL technology
• Eight outputs selectable as LVPECL or LVDS
• Input selectable: fundamental mode crystal or clock reference
• Supports fundamental mode crystals from 10MHz - 40MHz
• CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
• Input frequencies from 5MHz up to 800MHz
• Two independent output frequencies can be generated
• Output frequencies independent of each other and of input
• Output frequencies from 15.234MHz - 645MHz, and
975MHz - 1290MHz, (See Table 5D for details)
• RMS phase jitter at 125MHz (12kHz - 20MHz): 0.282ps (typical)
• RMS phase jitter at 156.25MHz (12kHz - 20MHz):
0.278ps (typical)
• Full 2.5V or 3.3V power supply
• I2C programming interface
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
• VCC / VCCA / VCCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V (LVPECL only)
2.5V / 2.5V / 2.5V
Pin Assignment
VEE_B
SCLK
SDATA
VEE
VCCA
LOCK
VEE
VCC
CLK_SEL
VEE_A
30 29 28 27 26 25 24 23 22 21
31 20
32 19
33
IDT8T49N524I
18
34 40 Lead VFQFN 17
35 6mm x 6mm x 0.925mm 16
36 4.65mm x 4.65mm EPad 15
37
NL Package
14
38
Top View
13
39 12
40 11
1 2 3 4 5 6 7 8 9 10
FSEL1
VCC
VEE
ADDR_SEL
FSEL0
nCLK
CLK
VEE
XTAL_OUT
XTAL_IN
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
1
©2014 Integrated Device Technology, Inc.
1 page  
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Function Tables
Table 4A. Frequency Select Table
FSEL1
FSEL0
Pre-scaler
Ratio
0 (default) 0 (default)
P
01
P
10
P
11
Feedback
Divider Ratio
MINT0
MINT1
MINT2
QAn Operation
NINTA_0
NFRACA_0
NINTA_1
NFRACA_1
NINTA_2
NFRACA_2
Reserved
QBn Operation
NINTB
NFRACB
NINTB
NFRACB
NINTB
NFRACB
Table 4B. I2C Register Function Descriptions
Bits Name
MINTn[7:0]
Integer Feedback Divider Register n
(n = 0...2)
P[1:0]
Input Divider Register
NINTA_n[5:0]
NFRACA_n[15:0]
Output Divider A - Integer Portion n
(n = 0...2)
Output Divider A - Fractional Portion
(n = 0...2)
NINTB[5:0]
Output Divider B - Integer Portion
NFRACB[15:0]
Output Divider B - Fractional Portion
CPn[1:0]
PLL Bandwidth n (n = 0...2)
OE_Qxx
Output Enable
LVDS_SEL
Output Style
PLL_BYPASS
DOUBLER_
ENABLE
DIVA_BYPASS
DIVB_BYPASS
DIVA_INT
DIVB_INT
PLL Bypass
Input Doubler
Bypass Output Divider A
Bypass Output Divider B
Divider A Integer Mode
Divider B Integer Mode
Function
Sets the integer feedback divider value. See Table 5B for the feedback
divider coding.
Sets the PLL input divider. The divider value has the range of 1, 2, 4 and
8. See Table 5C for the divider coding.
Sets the integer portion of the output divider A. See Table 5D for the
output divider coding.
Sets the fractional portion of the output divider A. See Table 5D for the
output divider coding.
Sets the integer portion of the output divider B. See Table 5D for the
output divider coding.
Sets the fractional portion of the output divider B. See Table 5D for the
output divider coding.
Sets the FemtoClock® NG PLL Charge Pump current to support the
selected operating frequency. See Table 5E.
Sets the desired output to Active or High impedance.
0 = Output is high-impedance (default)
1 = Output is active.
Selects differential output style
0 = LVPECL (default)
1 = LVDS
Bypasses PLL. Input to phase detector is routed through output dividers
A and B to the output fanout buffers. Dividers should be programmed for
integer divide operation (DIVA_INT = DIVB_INT = 0) for proper operation.
Enables the input frequency doubler.
0 = Input frequency presented directly to PLL
1 = Input frequency doubled before PLL (default)
Bypasses output divider A. QAn output frequency is VCO/2.
Bypasses output divider B. QBn output frequency is VCO/2.
Disables fractional portion of divider A. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
Disables fractional portion of divider B. Setting this bit will provide better
phase noise performance in cases where the fractional portion is 0.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
5
©2014 Integrated Device Technology, Inc.
5 Page 
IDT8T49N524I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS DUAL 4-OUTPUT FRACTIONAL CLOCK GENERATOR
Table 7F. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
VIH Input High Voltage
VCC = 3.3V
VCC = 2.5V
2
1.7
VIL Input Low Voltage
VCC = 3.3V
VCC = 2.5V
-0.3
-0.3
SCLK,
SDATA
VCC = VIN = 3.465V or 2.625V
IIH
Input
High Current FSEL[1:0],
CLK_SEL,
VCC = VIN = 3.465V or 2.625V
ADDR_SEL
VCC + 0.3
VCC + 0.3
0.8
0.7
5
150
SCLK,
SDATA
VCC = 3.465V or 2.625V, VIN = 0V
-150
IIL
Input
Low Current FSEL[1:0],
CLK_SEL,
VCC = 3.465V or 2.625V, VIN = 0V
-5
ADDR_SEL
Units
V
V
V
V
µA
µA
µA
µA
Table 7G. Differential DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
IIH
Input
High Current
CLK, nCLK
VCC = VIN = 3.465V or 2.625V
150 µA
IIL
Input
nCLK
Low Current CLK
VCC = 3.465V or 2.625V, VIN = 0V
VCC = 3.465V or 2.625V, VIN = 0V
-150
-5
VPP
Peak-to-Peak Voltage:
NOTE 1
0.15
µA
µA
1.3 V
VCMR
Common Mode Input
Voltage; NOTE 1, NOTE 2
VEE + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less then -0.3V.
NOTE 2: Common mode input voltage is at the crosspoint.
Table 7H. LVPECL DC Characteristics, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage
Swing
VCCO_X – 1.1
VCCO_X – 2.0
0.6
VCCO_X – 0.75
VCCO_X – 1.6
1.0
V
V
V
NOTE: VCCO_X denotes VCCO_A and VCCO_B.
NOTE 1: Outputs terminated with 50 to VCCO_X – 2V.
IDT8T49N524NLGI REVISION A JANUARY 23, 2014
11
©2014 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT8T49N524I.PDF ] | |
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