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PDF IDT8T49N366I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T49N366I | |
| Descripción | Triple Universal Frequency Translator | |
| Fabricantes | Integrated Device Technology | |
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FemtoClock® NG Triple Universal
Frequency TranslatorTM
IDT8T49N366I
DATA SHEET
General Description
The IDT8T49N366I is a triple PLL with FemtoClock® NG technology.
The IDT8T49N366I integrates low phase noise Frequency
Translation / Synthesis and Jitter attenuation. It includes alarm and
monitoring functions suitable for networking and communications
applications. The device has three fully independent PLLs. Each PLL
is able to generate any output frequency in the 0.98MHz - 312.5MHz
range and most output frequencies in the 312.5MHz - 1,300MHz
range (see Table 3 for details). A wide range of input reference
clocks may be used as the source for the output frequency.
Each PLL of IDT8T49N366I has three operating modes to support a
very broad spectrum of applications:
1) Frequency Synthesizer
• Synthesizes output frequencies from an external reference
clock REFCLK.
• Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
2) High-Bandwidth Frequency Translator
• Applications: PCI Express, Computing, General Purpose
• Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
• This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
3) Low-Bandwidth Frequency Translator
• Applications: Networking & Communications.
• Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I2C interface and the
device can be completely reconfigured.
Features
• Fourth generation FemtoClock® NG technology
• Three fully independent PLLs
• Universal Frequency TranslatorTM/Frequency Synthesizer and
Jitter attenuator
• Outputs are programmable as LVPECL or LVDS
• Programmable output frequency: 0.98MHz up to 1,300MHz
• Two differential inputs per PLL support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
• Input frequency range: 8kHz - 710MHz (Low-Bandwidth mode)
• Input frequency range: 16MHz - 710MHz (High-Bandwidth mode)
• REFCLK frequency range: 16MHz - 40MHz
• Input clock monitor on each PLL will smoothly switch between
redundant input references
• Factory-set register configuration for power-up default state
• Power-up default configuration
• Configuration customized via One-Time Programmable ROM
• Settings may be overwritten after power-up via I2C
• I2C Serial interface for register programming
• RMS phase jitter at 161.1328125MHz, using 40MHz REFCLK
(12kHz - 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
• RMS phase jitter at 400MHz, using 40MHz REFCLK
(12kHz - 20MHz): 333fs (typical), Synthesizer Mode (Integer FB)
• Full 2.5V ±5% supply mode
• -40°C to 85°C ambient operating temperature
• 10mm x 10mm CABGA package
• Lead-free (RoHS 6) packaging
IDT8T49N366AASGI REVISION A JUNE 28, 2013
1
©2013 Integrated Device Technology, Inc.
1 page  
IDT8T49N366I Data Sheet
FEMTOCLOCK® NG TRIPLE UNIVERSAL FREQUENCY TRANSLATORTM
Pin Assignment
J
Q0C
VEE_C
VCCO_C
nQ1B
LF1B
LF0B
VEE_B
nQ0B
Q0B
H
nQ0C
VEE_C
CLK0C nCLK0C LOCKC
Q1B
Rsvd
VEE_B
VEE_B
G
VEE_C
Rsvd
CLK1C nCLK1C SCLK
SDATA CLK1B CLK0B VCCO_B
F
LF0C
Q1C
VCC_C
CLK_
SELC
VCC_B
CLK_
SELB
nCLK1B nCLK0B
nQ1A
E LF1C
nc
VCCA_C
nc
REFCLK
PLL_
BYP
VCCA_B
LOCKB
LF1A
Bottom View
D nQ1C
nc
nc
nc
VCCO_A
CLK_
SELA
VCC_A
Q1A
LF0A
C nc
nc
nc
nc
LOCKA nCLK1A CLK1A Rsvd
VEE_A
B nc
nc
nc
nc
nc
nCLK0A CLK0A
VEE_A
nQ0A
A
nc
nc
nc
nc
nc
VCCA_A
VEE_A
Q0A
1 23456789
IDT8T49N366I Pin Map
80-Ball Lead
10mm x 10mm x1mm package body
CABGA Package
(bottom view)
IDT8T49N366AASGI REVISION A JUNE 28, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
IDT8T49N366I Data Sheet
FEMTOCLOCK® NG TRIPLE UNIVERSAL FREQUENCY TRANSLATORTM
Table 4E. Configuration-Specific Control Bits
Register Bits
Function
Q0_TYPEx
Determines the output type for output pair Q0, nQ0 for PLLx
0 = LVPECL
1 = LVDS
Q1_TYPEx
Determines the output type for output pair Q1, nQ1 for PLLx.
0 = LVPECL
1 = LVDS
Px[16:0]
Reference Pre-Divider for PLLx.
M1_x[16:0]
Integer Feedback Divider in Lower Feedback Loop for PLLx.
M_INTx[7:0]
Feedback Divider, Integer Value in Upper Feedback Loop for PLLx.
M_FRACx[17:0] Feedback Divider, Fractional Value in Upper Feedback Loop for PLLx.
Nx[10:0]
Output Divider for PLLx.
BWx[6:0]
Internal Operation Settings for PLLx.
Please use IDT IDT8T49N366I Configuration Software to determine the correct settings for these bits for the
specific configuration. Alternatively, please consult with IDT directly for further information on the functions of these
bits.The function of these bits are explained in Tables 4J and 4K.
Table 4F. Global Control Bits
Register Bits
Function
MODE_SELx[1:0]
PLL Mode Select for PLLx
00 = Low Bandwidth Frequency Translator
01 = Frequency Synthesizer
10 = High Bandwidth Frequency Translator
11 = High Bandwidth Frequency Translator
OE0x
Output Enable Control for Output 0 for PLLx.
0 = Output Q0, nQ0 disabled
1 = Output Q0, nQ0 enabled
OE1x
Output Enable Control for Output 1 for PLLx.
0 = Output Q1, nQ1 disabled
1 = Output Q1, nQ1 enabled
Rsvd
Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed
AUTO_MANx[1:0]
Selects how input clock selection is performed for PLLx.
00 = Manual Selection via pin only
01= Automatic, non-revertive
10 = Automatic, revertive
11= Manual Selection via register only
CLK_SELx
In manual clock selection via register mode for PLLx, this bit will command which input clock is selected. In the
automatic modes, this indicates the primary clock input. In manual selection via pin mode, this bit has no effect.
0 = CLK0
1 = CLK1
ADC_RATEx[1:0]
Sets the ADC sampling rate in Low-Bandwidth Mode as a fraction of the REFCLK input frequency for PLLx
00 = REFCLK Frequency / 16 when doubler is disabled
01 = REFCLK Frequency / 8 when doubler is disabled
10 = REFCLK Frequency / 4 (recommended) when doubler is disabled
11 = REFCLK Frequency / 2 when doubler is disabled
LCK_WINx[1:0]
Sets the width of the window in which a new reference edge must fall relative to the feedback edge for PLLx:
00 = 2usec (recommended), 01 = 4usec, 10 = 8usec, 11 = 16usec
DBL_REFCLKx
When set, this bit will double the frequency of the REFCLK input before applying it to the Phase-Frequency
Detector for PLLx
IDT8T49N366AASGI REVISION A JUNE 28, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT8T49N366I.PDF ] | |
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