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PDF IDT8T49N222I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T49N222I | |
| Descripción | Universal Frequency Translator | |
| Fabricantes | Integrated Device Technology | |
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DATA SHEET
FemtoClock® NG Universal Frequency
Translator
IDT8T49N222I
General Description
The IDT8T49N222I is a highly flexible FemtoClock® NG general
purpose, low phase noise Frequency Translator / Synthesizer with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate any output
frequency in the 7.29MHz to 833.33MHz range and most output
frequencies in the 925MHz to 1200MHz range (see Table 3A for
details). A wide range of input reference clocks and a range of
low-cost fundamental mode crystal frequencies may be used as the
source for the output frequency.
The IDT8T49N222I has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
• Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
• Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
2) High-Bandwidth Frequency Translator
• Applications: PCI Express, Computing, General Purpose
• Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
• This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
3) Low-Bandwidth Frequency Translator
• Applications: Networking & Communications.
• Translates any input clock in the 8kHz –710MHz frequency
range into any supported output frequency.
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
This device provides a factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by the customer and is programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I2C interface and the
device can be completely reconfigured. However, these settings
would have to be written every time the device powers-up.
Features
• Fourth generation FemtoClock® NG technology
• Universal Frequency Translator
• Zero ppm frequency translation
• Two outputs, individually programmable as LVPECL or LVDS
• Outputs may be individually set to use 2.5V or 3.3V output
levels
• Individually programmable output frequencies: 7.29MHz up to
1200MHz
• Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
• Input frequency range: 8kHz to 710MHz
• Hitless switching between inputs
• Crystal input frequency range: 16MHz to 40MHz
• Holdover support in the event both inputs fail
• One factory-set register configuration for power-up default state
• Configurations customized via One-Time Programmable ROM
• Settings may be overwritten after power-up via I2C
• I2C Serial interface for register programming
• RMS phase jitter at 156.25MHz, using a 40MHz crystal
(12kHz - 20MHz): 507fs (typical), Low Bandwidth Mode (FracN)
• Supports ITU-T G.8262 Synchronous Ethernet equipment slave
clocks (EEC option 1 and 2)
• Output supply voltage modes:
VCC/VCCA/VCCOx
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V (LVPECL only)
2.5V/2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Pin Assignment
CLK_ACTIVE
VEE
LF0
LF1
VEE
VEE
nc
VCCA
HOLDOVER
CLK0BAD
CLK1BAD
XTALBAD
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 IDT8T49N222I
22
40 48 Lead VFQFN
21
41 7.0mm x 7.0mm x 0.925mm, 20
42 package body 19
43 NL Package
18
44
45
Top View
17
16
46 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
VEE
nc
VCC
S_AO
S_A1
Reserved
nc
SCLK
SDATA
VCC
PLL_BYPASS
nc
IDT8T49N222BNLGI REVISION A MAY 13, 2013
1
©2013 Integrated Device Technology, Inc.
1 page  
IDT8T49N222I Data Sheet
FemtoClock® NG Universal Frequency Translator
Functional Description
The IDT8T49N222I is designed to provide two output frequencies
almost anywhere within its supported output frequency range
(7.29MHz to 1200MHz) from any input source in the supported input
frequency range (8kHz to 710MHz). It is capable of synthesizing
frequencies from a crystal or crystal oscillator source. The output
frequency is generated regardless of the relationship to the input
frequency. The output frequency will be exactly the required
frequency in most cases. In most others, it will only differ from the
desired frequency by a few ppb. IDT configuration software will
indicate the frequency error, if any. The IDT8T49N222I can translate
the desired output frequency from one of two input clocks. Again, no
relationship is required between the input and output frequencies in
order to translate to the output clock rate. In this frequency translation
mode, a low-bandwidth, jitter attenuation option is available that
makes use of an external fixed-frequency crystal or crystal oscillator
to translate from a noisy input source. If the input clock is known to
be fairly clean or if some modulation on the input needs to be tracked,
then the high-bandwidth frequency translation mode can be used,
without the need for the external crystal.
The input clock references and crystal input are monitored
continuously and appropriate alarms are raised both as register bits
and hard-wired pins in the event of any out-of-specification conditions
arising. Clock switching is supported in manual, revertive &
non-revertive modes.
The IDT8T49N222I has one factory-programmed configuration that
sets the default operating state after reset. These defaults may be
over-written by I2C register access at any time, but those over-written
settings will be lost on power-down. Please contact IDT if a specific
set of power-up default settings is desired. Users that have a custom
configuration programmed may not require I2C access.
Please make use of IDT-provided configuration tools to determine the
best operating settings for the desired configurations of the device.
Please refer to the Universal Frequency Translator Family
Programming Guide if further details are required.
Operating Modes
The IDT8T49N222I has three operating modes which are set by the
MODE_SEL[1:0] bits. There are two frequency translator modes -
low bandwidth and high bandwidth and a frequency synthesizer
mode.
Please make use of IDT-provided configuration applications to
determine the best operating settings for the desired configurations
of the device.
Output Dividers & Supported Output Frequencies
The internal VCO is capable of operating in a range from 1.850GHz
up to 2.5GHz. The output divider stages N0[7:0] and N1[7:0] are
limited to selection of integers from 2 to 254. Please refer to Table 3A
for the recommended values of N applicable to the desired output
frequency.
Table 3A. Output Divider Settings & Frequency Ranges*
Register
Setting
Nn[7:0]
Frequency
Divider
Nn
Minimum
fOUT
(MHz)
Maximum
fOUT
(MHz)
0000000x
Not Supported
00000010
2
925.00
1200.00
00000011
3
616.67
833.33
00000100
4
462.50
625.00
00000101
5
370.00
500.00
00000110
6
308.33
416.67
00000111
7
264.29
357.14
00001000
8
231.25
312.50
00001001
9
205.56
277.78
00001010
10
185.00
250.00
...
11111110
254
7.29
9.84
*NOTE: Frequency ranges for other N output dividers are possible.
Contact IDT Factory for special cases.
In addition to the above output divider settings, it is possible for either
or both of the outputs to present a copy of the currently active input
reference frequency by asserting the appropriate BYPn register bit.
IDT8T49N222BNLGI REVISION A MAY 13, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
IDT8T49N222I Data Sheet
FemtoClock® NG Universal Frequency Translator
Table 4E. Control Bits
Register Bits
Function
Q0_TYPE
Determines the output type for output pair Q0, nQ0.
0 = LVPECL (Default)
1 = LVDS
Q1_TYPE
Determines the output type for output pair Q1, nQ1.
0 = LVPECL (Default)
1 = LVDS
BYP0
Bypass Input to output Q0.
0 = Use result of output divider N0 (Default)
1 = Drive currently active input reference frequency on output
BYP1
Bypass Input to output Q1.
0 = Use result of output divider N1 (Default)
1 = Drive currently active input reference frequency on output
P[16:0]
Reference Pre-Divider.
M1[16:0]
Integer Feedback Divider in Lower Feedback Loop.
M_INT[7:0]
Feedback Divider, Integer Value in Upper Feedback Loop.
M_FRAC[17:0]
Feedback Divider, Fractional Value in Upper Feedback Loop.
N0[7:0]
Output Divider for Q0, nQ0.
N1[7:0]
Output Divider for Q1, nQ1.
BW[6:0]
Internal Operation Settings.
Please use IDT IDT8T49N222I Configuration Software to determine the correct settings for these bits for the
specific configuration. Alternatively, please consult with IDT directly for further information on the functions of these
bits.The function of these bits is explained in Tables 4H and 4I.
Re-calibrate
This bit is asserted to force a VCO calibration cycle. The bit needs to be returned to ‘0’ to resume normal operation.
This is only needed if the P[16:0], M_INT[7:0] or M_FRAC[17:0] registers are changed after power-up. The device
automatically calibrate the VCO on power-up.
Rsvd
Reserved bits - user should write a ‘0’ to these bit positions if a write to these registers is needed.
IDT8T49N222BNLGI REVISION A MAY 13, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
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