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PDF IDT8T49N004I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T49N004I | |
| Descripción | LVPECL/LVDS Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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Programmable FemtoClock® NG LVPECL/LVDS
Clock Generator with 4-Outputs
IDT8T49N004I
DATASHEET
General Description
The IDT8T49N004I is a four output Clock Generator with selectable
LVDS or LVPECL outputs. The IDT8T49N004I can generate any one
of four frequencies from a single crystal or reference clock. The four
frequencies are selected from the Frequency Selection Table (Table
3A) and are programmed via I2C interface. The four predefined
frequencies are selected in the user application by two frequency
selection pins. Note the desired programmed frequencies must be
used with the corresponding crystal or clock frequency as indicated
in Table 3A.
Excellent phase noise performance is maintained with IDT’s Fourth
Generation FemtoClock® NG PLL technology, which delivers
sub-400fs RMS phase jitter.
Features
• Fourth Generation FemtoClock NG PLL technology
• Four selectable LVPECL or LVDS outputs via I2C
• CLK, nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, HCSL
• FemtoClock NG VCO Range: 1.91GHz - 2.5GHz
• RMS phase jitter at 156.25MHz (12kHz - 20MHz):
228fs (typical)
• RMS phase jitter at 156.25MHz (10kHz - 1MHz): 175fs (typical)
• Full 2.5V or 3.3V power supply
• I2C programming interface
• PCI Express (2.5Gb/s), Gen 2 (5Gb/s), and Gen 3 (8Gb/s)
jitter compliant
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Pin Assignment
24 23 22 21 20 19 18 17
SCLK 25
16 VCC
SDATA 26
VEE 27
15 VEE
14 FSEL0
VCCA 28
13 nCLK
LOCK 29
12 CLK
VEE 30
11 VEE
VCC 31
10 XTAL_OUT
CLK_SEL 32
9 XTAL_IN
12 34 5 67 8
IDT8T49N004I
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm E-Pad
NL Package
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
1
©2013 Integrated Device Technology, Inc.
1 page  
IDT8T49N004I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS
Output Frequencies
(MHz)
Input Frequency or
Crystal Frequency
(MHz)
Input Clock
Divider
P
Input Clock
Prescaler
PS
Feedback
Divider
M
Output Divider
N
VCO
Frequency
(MHz)
322.265625
25.78125
2
x1 150
6 1933.59375
375 25 1 x1 90 6 2250
400 25 1 x2 40 5 2000
425
26.5625
1 x2 40 5 2125
491.52
30.72
1 x2 32 4 1966.08
30.72
1 x2 40 4 2457.6
614.4
122.88
2 x1 40 4 2457.6
153.6
5 x2 40 4 2457.6
622.08
19.44
1 x2 64 4 2488.32
625 25 1 x2 50 4 2500
1228.88
30.72
1 x2 40 2 2457.6
NOTE: Each device supports 4 output frequencies (with related input or crystal value) as selected from this table Register Settings.
NOTE: XTAL operation: fOUT = fREF * PS * M / N; CLK, nCLK input operation: fOUT = (fREF / P) * PS * M / N.
Table 3B. I2C Register Map
Register
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Binary
Register
Address
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
D7 D6
D5
M0[8]
M0[7]
M0[6]
M1[8]
M1[7]
M1[6]
M2[8]
M2[7]
M2[6]
M3[8]
M3[7]
M3[6]
unused
N0[6]
N0[5]
unused
N1[6]
N1[5]
unused
N2[6]
N2[5]
unused
N3[6]
N3[5]
unused
BYPASS0
PS0[1]
unused
BYPASS1
PS1[1]
unused
BYPASS2
PS2[1]
unused
BYPASS3
PS3[1]
reserved LVDS_SEL0[Q3] LVDS_SEL0[Q2]
reserved LVDS_SEL1[Q3] LVDS_SEL1[Q2]
reserved LVDS_SEL2[Q3] LVDS_SEL2[Q2]
reserved LVDS_SEL3[Q3] LVDS_SEL3[Q2]
reserved
OE0[Q3]
OE0[Q2]
reserved
OE1[Q3]
OE1[Q2]
reserved
OE2[Q3]
OE2[Q2]
reserved
OE3[Q3]
OE3[Q2]
reserved
reserved
reserved
unused
unused
unused
unused
unused
unused
unused
unused
unused
Register Bit
D4
M0[5]
M1[5]
M2[5]
M3[5]
N0[4]
N1[4]
N2[4]
N3[4]
PS0[0]
PS1[0]
PS2[0]
PS3[0]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
unused
unused
D3
M0[4]
M1[4]
M2[4]
M3[4]
N0[3]
N1[3]
N2[3]
N3[3]
P0[1]
P1[1]
P2[1]
P3[1]
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
unused
unused
unused
D2 D1 D0
M0[3]
M0[2]
M0[1]
M1[3]
M1[2]
M1[1]
M2[3]
M2[2]
M2[1]
M3[3]
M3[2]
M3[1]
N0[2]
N0[1]
N0[0]
N1[2]
N1[1]
N1[0]
N2[2]
N2[1]
N2[0]
N3[2]
N3[1]
N3[0]
P0[0]
CP0[1]
CP0[0]
P1[0]
CP1[1]
CP1[0]
P2[0]
CP2[1]
CP2[0]
P3[0]
CP3[1]
CP3[0]
LVDS_SEL0[Q1] LVDS_SEL0[Q0] reserved
LVDS_SEL1[Q1] LVDS_SEL1[Q0] reserved
LVDS_SEL2[Q1] LVDS_SEL2[Q0] reserved
LVDS_SEL3[Q1] LVDS_SEL3[Q0] reserved
OE0[Q1]
OE0[Q0]
reserved
OE1[Q1]
OE1[Q0]
reserved
OE2[Q1]
OE2[Q0]
reserved
OE3[Q1]
OE3[Q0]
reserved
reserved
unused
unused
unused
unused
unused
unused
unused
unused
unused
unused
unused
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
5
©2013 Integrated Device Technology, Inc.
5 Page 
IDT8T49N004I Data Sheet
PROGRAMMABLE FEMTOCLOCK® NG LVPECL/LVDS CLOCK GENERATOR WITH 4-OUTPUTS
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High
Voltage
SCLK, SDATA,
CLK_SEL, FSEL[1:0]
VCC = 3.3V
VCC = 2.5V
2
1.7
SCLK, SDATA, CLK_SEL
VIL
Input Low
Voltage
SCLK, SDATA, CLK_SEL
FSEL[1:0]
VCC = 3.3V
VCC = 2.5V
VCC = 3.3V or 2.5V
-0.3
-0.3
IIH
Input
SCLK, SDATA
High Current CLK_SEL, FSEL[1:0]
VCC = VIN = 3.465V or 2.625V
VCC = VIN = 3.465V or 2.625V
IIL
Input
SCLK, SDATA
Low Current CLK_SEL, FSEL[1:0]
VCC = 3.465V or 2.625V, VIN = 0V
VCC = 3.465V or 2.625V, VIN = 0V
-150
-5
Output
LOCK
VOH High Voltage;
NOTE 1
LOCK
VCCO = 3.465V
VCCO = 2.625V
2.6
1.8
VCC + 0.3
VCC + 0.3
0.8
0.7
0.5
5
150
V
V
V
V
V
µA
µA
µA
µA
V
V
Output
VOL Low Voltage; LOCK
NOTE 1
VCCO = 3.465V or 2.625V
0.5 V
NOTE 1: Outputs terminated with 50 to VCCO/2. In the Parameter Measurement Information Section, see Output Load Test Circuit Diagrams.
Table 4D. Differential DC Characteristics, VCC = VCCO = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
IIH
Input
High Current
CLK, nCLK
VCC = VIN = 3.465V or 2.625V
150
IIL
VPP
VCMR
Input
Low Current
nCLK
CLK
Peak-to-Peak Voltage
Common Mode Input Voltage;
NOTE 1
VCC = 3.465V or 2.625V, VIN = 0V
VCC = 3.465V or 2.625V, VIN = 0V
-150
-5
0.15
VEE
1.3
VCC – 0.85
NOTE 1: Common mode input voltage is at the cross point.
Units
µA
µA
µA
V
V
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO – 1.1
VCCO – 2.0
0.6
NOTE 1: Outputs termination with 50 to VCCO – 2V.
Maximum
VCCO – 0.75
VCCO – 1.6
1.0
Units
V
V
V
IDT8T49N004ANLGI REVISION A OCTOBER 15, 2013
11
©2013 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT8T49N004I.PDF ] | |
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