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Número de pieza IDT8T33FS314I
Descripción LVPECL/ECL Fanout Buffer
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Low Skew, 1-to-4 Differential-to-2.5V, 3.3V IDT8T33FS314I
LVPECL/ECL Fanout Buffer
DATA SHEET
General Description
The IDT8T33FS314I is a low skew 1-to-4 Differential Fanout Buffer,
designed with clock distribution in mind, accepting two clock sources
into an input MUX. The MUX is controlled by a CLK_SEL pin. This
makes the IDT8T33FS314I very versatile, in that, it can operate as
both a differential clock buffer as well as a signal-level translator and
fanout buffer.
The device is designed on a SiGe process and can operate at
frequencies in excess of 2.7GHz. This ensures negligible jitter
introduction to the timing budget which makes it an ideal choice for
distributing high frequency, high precision clocks across back planes
and boards in communication systems. Internal temperature
compensation guarantees consistent performance across various
platforms.
Features
Four differential ECL/LVPECL level outputs
One differential ECL/LVPECL or single-ended input (CLKA)
One differential HSTL or single-ended input (CLKB)
Maximum output frequency: 2.7GHz
Additive phase jitter, RMS: 0.114ps (typical) @ 156.25MHz
Output skew: 50ps (maximum)
LVPECL and HSTL mode operating voltage supply range:
VCC = 2.5V±5% or 3.3V±5%, VEE = 0V
ECL mode operating voltage supply range:
VEE = -3.3V±5% or -2.5V±5%, VCC = 0V
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
VCC
CLKA Pulldown
nCLKA Pullup/Pulldown
VCC
CLKB Pulldown
nCLKB Pullup/Pulldown
VEE
CLK_SEL Pulldown
VEE
0
1
VEE
Pin Assignment
VCC 1
20 VCC
Q0 nc 2 19 Q0
nQ0
VCC 3
18 nQ0
CLK_SEL 4 17 Q1
Q1 CLKA 5 16 nQ1
nQ1 nCLKA 6 15 Q2
CLKB 7 14 nQ2
Q2
nQ2
nCLKB
VEE
VCC
8
9
10
13 Q3
12 nQ3
11 VCC
Q3
nQ3
IDT8T33FS314I
20-Lead 209-MIL SSOP
5.3mm x 7.2mm x 1.75mm body package
PY Package
Top View
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm body package
PG Package
Top View
IDT8T33FS314PGI REVISION A MARCH 7, 2014
1
©2014 Integrated Device Technology, Inc.

1 page




IDT8T33FS314I pdf
IDT8T33FS314I Data Sheet
LOW SKEW, 1-to-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
AC Electrical Characteristics
Table 4. AC Characteristics, (LVPECL/HSTL), VCC = 3.3V ±5% or 2.5V ±5%, VEE = 0V, or
(ECL) VEE = -3.3V ±5% or -2.5V ±5%, VCC = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VPP
VCMR
Differential Input Voltage; NOTE 1
Differential Input Crosspoint Voltage;
NOTE 2
0.15
VEE + 1.0
fCLK Input Frequency; NOTE 3
tPD
Propagation Delay, CLKA or CLKB to
Output Pair; NOTE 4
230
VDIF
HSTL Differential Input Voltage;
NOTE 5
0.4
VX
HSTL Input Differential Crosspoint
Voltage; NOTE 6
VEE + 0.01
VO(pp)
tsk(o)
Differential Output Voltage
(peak-to-peak)
Output Skew
ƒOUT < 300MHz
ƒOUT < 1.5GHz
0.45 0.88
0.3 0.74
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
156.25MHz, @ 3.3V,
1.875MHz – 20MHz
312.5MHz @ 3.3V,
1.875MHz – 20MHz
0.114
0.052
tsk(p) Output Pulse Skew; NOTE 7
660MHz
tR / tF
Output Rise/Fall Time
20% to 80%
0.05
Maximum
1.3
VCC - 0.3
2.7
650
Units
V
V
GHz
ps
1.0 V
VCC - 1.0
0.95
0.95
50
V
V
V
ps
ps
ps
75 ps
0.3 ns
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: VPP is the minimum differential ECL/LVPECL input voltage swing required to maintain AC characteristics including tPD and
device-to-device skew.
NOTE 2: VCMR is the crosspoint of the differential ECL/LVPECL input signal. Normal AC operation is obtained when the crosspoint is within
the VCMR range and the input swing lies within the VPP specification. Violation of VCMR or VPP impacts the device propagation delay, device
and part-to-part skew.
NOTE 3: The IDT8T33FS314 is fully operational up to 2.7GHz and is characterized up to 1.5GHz.
NOTE 4: Propagation delay specified for output rise and fall times less than 5ns.
NOTE 5: VDIF is the minimum differential HSTL input voltage swing required to maintain AC characteristics including tPD and device-to-
device skew.
NOTE 6: VX is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VX
range and the input swing lies within the VDIF specification. Violation of VX or VDIF impacts the device propagation delay, device and
part-to-part skew.
NOTE 7: Output pulse skew is the absolute value of the difference of the propagation delay times: tPLH – tPHL .
IDT8T33FS314PGI REVISION A MARCH 7, 2014
5
©2014 Integrated Device Technology, Inc.

5 Page





IDT8T33FS314I arduino
IDT8T33FS314I Data Sheet
LOW SKEW, 1-to-4 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
2.5V Differential Clock Input Interface
CLKx/nCLKx accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both VO(PP) and VOH must meet the VPP and
VCMR input requirements. Figure 3A to Figure 3E show interface
examples for the CLKx/nCLKx input driven by the most common
driver types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50
Zo = 50
LVHSTL
IDT Open Emitter
LVHSTL Driver
2.5V
CLK
R1 R2
5050
nCLK
Differential
Input
Figure 3A. CLKx/nCLKx Input Driven by an
IDT Open Emitter LVHSTL Driver
2.5V
LVPECL
Zo = 50
Zo = 50
2.5V
CLK
R1 R2
5050
nCLK
Differential
Input
R3
18
Figure 3B. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
2.5V
LVPECL
Zo = 50
Zo = 50
2.5V
R3
250
R4
250
2.5V
CLK
R1
62.5
R2
62.5
nCLK
Differential
Input
2.5V
LVDS
Zo = 50
Zo = 50
2.5V
R1
100
CLK
nCLK
Differential
Input
Figure 3C. CLKx/nCLKx Input Driven by a
2.5V LVPECL Driver
Figure 3D. CLKx/nCLKx Input Driven by a
2.5V LVDS Driver
2.5V
2.5V
*R3 33Ω
Zo = 50Ω
Zo = 50Ω
HCSL
*R4 33Ω
*Optional – R3 and R4 can be 0Ω
R1
50Ω
CLK
nCLK
R2
50Ω
Differential
Input
Figure 3E. CLKx/nCLKx Input Driven by a
2.5V HCSL Driver
IDT8T33FS314PGI REVISION A MARCH 7, 2014
11
©2014 Integrated Device Technology, Inc.

11 Page







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