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Número de pieza XR81411
Descripción LVCMOS/LVDS/LVPECL Clock Synthesizer
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XR81411
Universal Quad Clock - High Frequency
LVCMOS/LVDS/LVPECL Clock Synthesizer
General Description
The XR81411 is a Quad Clock synthesizer with 4 independent PLLs in a
compact LGA-45 package. Each synthesizer generates ANY frequency in
the range of 10 MHz to 800MHz by utilizing a highly flexible delta sigma
modulator and a wide ranging VCO. The outputs are independently configu-
rable for single ended LVCMOS or differential LVDS or LVPECL. The clock
outputs have very low typical phase noise jitter of sub 0.6ps RMS, while
consuming extremely low power. The XR81411 uses a single reference and
provides 4 independent outputs that can be configured as needed to sup-
port a wide variety of applications.
Each of the XR81411’s 4 independent PLLs include an integer/fractional
divider, LVCMOS/LVDS/LVPECL output driver, 3.3V/2.5V supply, and gener-
ates one of four selectable output frequencies from a single reference. The
XR81411 is optimized for use with a fundamental mode 10MHz to 60MHz
crystal (or system clock) and generates a selection of output frequencies
ranging from 10MHz to 800MHz in either integer or fractional mode. In frac-
tional mode, frequency resolution of better than 2Hz steps can be achieved.
The application diagram below shows a typical LAN synthesizer configura-
tion with any standard crystal oscillating in fundamental mode.
The typical phase noise plot below shows the jitter integrated over the
12KHz to 20MHz range that is widely used in these systems.
FEATURES
• Small footprint 5mm x 5mm LGA package
• Configurable Outputs - As differential LVPECL/
LVDS pair or as a single ended LVCMOS.
• Crystal oscillator interface which can also be
overdriven using a single-ended reference clock
• Output frequency range: 10MHz - 800MHz
• Crystal/input frequency: 10MHz to 60MHz, paral-
lel resonant crystal
• VCO range: 2GHz - 3GHz
• Phase jitter @
- 125MHz (12KHz - 20MHz): <0.6ps RMS
- 125MHz (1.875MHz -20MHz): <0.25ps RMS
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) package
APPLICATIONS
• 10GE, GE LAN/WAN
• 2.5G/10G SONET/SDH/OTN
• xDSL, PCIe
• Low-jitter Clock Generation
• Synchronized clock systems
Ordering Information – Last Page
Typical Application Diagram and Performance
25MHz
XR81411
Xt al_In
Q1
Q1
Xtal_Out Q2
Q2
Control
Pins
Q3
Q3
Q4
Q4
LVCMOS *
(10-200MHz)
LVPECL *
(10-800MHz)
LVDS *
(10-800MHz)
LVCMOS *
(10-200MHz)
(* Any Frequency, Any Output Format)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
1.E+02
PHASE NOISE
Qs=125MHz CMOS Output
1.E+03
1.E+04
1.E+05
1.E+06
OFFSET FREQUENCY(Hz)
1.E+07
Q1=125MHz
Q2=125MHz
Q3=125MHz
Q4=125MHz
© 2014 Exar Corporation
1 / 15
exar.com/XR81411
Rev 1A

1 page




XR81411 pdf
Pin Assignments
XR81411
Pin No.
Pin Name
1 Q1
2 Q1
3 VDD1C
4 XTAL_IN
5 XTAL_OUT
6 FSEL1_4
7 FSEL0_4
8 NC
9 GND
10 OE_4
11 VDD4C
12 Q4
13 Q4
14 VDD4D
15 FSEL1_3
16 FSEL0_3
17 NC
18 GND
19 OE_3
20 VDD3
21 Q3
22 Q3
23 FSEL1_2
24 FSEL0_2
25 NC
26 OE_2
27 GND
Type
Description
Output
Channel 1 Positive Clock Output
Output
Channel 1Inverted Clock Output
Power
Channel 1 Core Supply Voltage
Input
Crystal oscillator input.
Output
Crystal oscillator output (external reference input)
Input
Channel 4 Output frequency select 1, MSB (LVCMOS/LVTTL input).
(900Kpull-dwn)
Input
Channel 4 Output frequency select 0, LSB (LVCMOS/LVTTL input).
(900Kpull-dwn)
No Connection Do not connect.
GND
Ground.
Input
(900Kpull-up)
Channel 4 Output enable - LVCMOS/LVTTL active high input.
Outputs are enabled when OE = high. Outputs are disabled when OE = low.
Power
Channel 4 Core Supply Voltage. )
Output
Channel 4 Positive Clock Output.
Output
Channel 4 Inverted Clock Output.
Power
Channel 4 Driver Supply Voltage.)
Input
Channel 3 Output frequency select 1, MSB (LVCMOS/LVTTL input).
(900Kpull-dwn)
Input
Channel 3 Output frequency select 0, LSB (LVCMOS/LVTTL input).
(900Kpull-dwn)
No Connection Do not connect.
GND
Ground.
Input
(900Kpull-up)
Channel 3 Output enable - LVCMOS/LVTTL active high input.
Outputs are enabled when OE = high. Outputs are disabled when OE = low.
Power
Channel 3 Core and Driver Supply Voltage.
Output
Channel 3 Positive Clock Output.
Output
Channel 3 Inverted Output.
Input
Channel 2 Output frequency select 1, MSB (LVCMOS/LVTTL input).
(900Kpull-dwn)
Input
Channel 2 Output frequency select 0, LSB (LVCMOS/LVTTL input).
(900Kpull-dwn)
No Connection Do not connect.
Input
(900Kpull-up)
Channel 2 Output enable - LVCMOS/LVTTL active high input.
Outputs are enabled when OE = high. Outputs are disabled when OE = low.
GND
Ground.
© 2014 Exar Corporation
5 / 15
exar.com/XR81411
Rev 1A

5 Page





XR81411 arduino
XR81411
+VDD/2
Vcc
LVCMOS
Output
Vss
-VDD/2
Z = 50

Scope
Input Stage
The XR81411’s input is designed to be used with a parallel
resonant crystal in the range of 10MHz to 60MHz. It can
also be overdriven by an external single-ended source.
The XR81411 uses a Pierce oscillator circuit that has a vari-
able gain control and selectable capacitor load options on
each of the XTAL pins.
Figure 11: XR81411 Split Supply LVCMOS Output Termination
Output Signal Timing Definitions
The following diagrams clarify the common definitions of
the AC timing measurements.
C1
XTAL_In
XR81411
G
Q
80%
20%
nQ
tR
80%
VSWING
20%
tF
Figure 12: Output Rise/Fall Time and Swing
XTAL_Out
C2
REF
Figure 14: XR81411 Input Stage
The XR81411 input stage also has the ability to use a
startup state that can configure the gain and capacitor load-
ing conditions different from normal operation to improve
crystal startup time.
Q
nQ
tPW
tPERIOD
odc =
tPW
tPERIOD
x 100%
Figure 13: Output Period and Duty Cycle
PLL Stages
Each of the independent PLLs within the XR81411 can be
configured operate at any of four distinct settings. The PLL
takes the REF output from the Input stage and can produce
any frequency from 10MHz to 800MHz. The PLL can be
configured for integer or fractional operation. The internal
calibration circuitry of the XR81411 will optimize the config-
uration of the VCO, LPF and divider (DSM, N and Output)
settings for the input and output frequencies chosen.
Configurable Attributes
The XR81411 is highly adaptable and can be configured for
many different applications. The device performance of the
input stage, PLL stages and the output stages can be
adjusted (programmed by the factory) to meet any number
of application requirements.
REF
Phase
Detector
Charge
Pump
Lowpass
Filter
Post
Divider
Out’
Control
DSM
N
Divider
Figure 15: XR81411 PLL
© 2014 Exar Corporation
11 / 15
exar.com/XR81411
Rev 1A

11 Page







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