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PDF IJW120R100T1 Data sheet ( Hoja de datos )
| Número de pieza | IJW120R100T1 | |
| Descripción | Silicon Carbide-Junction Field Effect Transistor | |
| Fabricantes | Infineon | |
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SiC- JFET
Silicon Carbide- Junction Field Effect Transistor
CoolSiC™
1200 V CoolSiC™ Power Transistor
IJW120R100T1
Final Datasheet
Rev. 2.0, <2013-09-11>
Power Management & Multimarket
1 page  
Silicon Carbide JFET
IJW120R100T1
Application considerations
1.3 Device characteristics
1.3.1 Gate voltage window
The gate electrode of the JFET shows, in contrary to isolated MOSFET concepts, a bipolar pn-junction like
characteristic: it get’s forward biased at around +2.5 V, hence a bipolar current will flow into the gate once the
gate- to- source voltage exceeds 2.5 V. This is uncritical and may be used to turn-on the device faster than with
the recommended 0 V turn-on. At 25 °C the threshold voltage of the channel can vary between -12 V and -15 V
(Figure 3: VGS(th)=f(Tj ) parameter: IGSS). The products will be delivered within three groups (bin1, bin2, bin3) of
1 V range each. For paralleling, it is only allowed to parallel devices from the same bin. The use of devices from
different bins for paralleling leads to different thermal device behavior. At a voltage of around -23 V the gate- to-
source junction enters reverse breakdown, which leads to a temperature dependend bipolar current flow across
the junction. In pure voltage driven turn-on and turn-off the lower gate voltage should stay within the window
between the pinch-off (threshold) and the punch-through (increased leakage) voltage. For fast and safe turn-off
it is strongly recommended to move the lower gate voltage level as close as possible to the punch-through
threshold.
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-50
bin 2
Figure 3: VGS(th)=f(Tj ) parameter: IDSS=10 µA
gate off window
25 Tj [°C]
100
bin 1
bin 3
175
1.3.2 Controllability
The JFET can be well controlled through its miller plateau with an external gate resistor (Figure 4: dVoff/ dt=
f(IDS), dVon/ dt= f(IDS), dIoff/ dt= f(IDS), dIon/ dt= f(IDS) parameter: Tj=25 °C, RG, external). Especially dI/ dt is saturating
at high current levels. This helps to avoid voltage overshoots in peak current conditions. It is strongly
recommended to use very low turn-off gate resistors (down to zero Ohm external gate resistor) to achive
maximum performance from the device as well as to avoid any parasitic dV/dt or dI/dt coupled turn-on effects.
As shown in the maximum rating division of the datasheet the external gate loop resistance should be lower
than 5.1 Ω.
Figure 4: dVoff/ dt= f(IDS), dVon/ dt= f(IDS), dIoff/ dt= f(IDS), dIon/ dt= f(IDS) parameter: Tj=25 °C, RG, external
Final Datasheet
5 Rev. 2.0, <2013-09-11>
5 Page 
Table 11
Typical transfer characteristic- linear scale
Silicon Carbide JFET
IJW120R100T1
Electrical characteristics diagrams
Typical transfer characteristic- logarithmic scale
140
25°C
120
100
80
175 °C
60
40
20
0
-14 -12 -10 -8 -6 -4 -2 0 2
VGS [V]
1 000
100
T = 25 °C
10
1
-14 -12 -10 -8 -6 -4 -2 0 2
VGS [A]
IDS= ƒ(VGS ); VDS= 30 V; parameter: Tj; Vpi 25 °C
IDS= ƒ(VGS ); VDS= 30 V; parameter: Tj; Vpi 25 °C
Table 12
Gate voltage window
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-50
bin 2
gate off window 1)
25 Tj [°C] 100
bin 1
bin 3
175
Body diode characteristics
50 0 V -5 V
40
30
20
10
0
0
-10 V
-15 V
-20 V
246
VDS (V)
8 10
VGS(th) = ƒ(Tj ), VDS=40 V; parameter: IDSS=10 µA
1) lower gate voltage leads to increased leakage current
ISD= ƒ(VDS ); Tj= 25 °C parameter: VGS
Final Datasheet
11 Rev. 2.0, <2013-09-11>
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IJW120R100T1.PDF ] | |
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