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PDF HCPL-0723 Data sheet ( Hoja de datos )
| Número de pieza | HCPL-0723 | |
| Descripción | 50 MBd 2 ns PWD High Speed CMOS Optocoupler | |
| Fabricantes | Avago | |
| Logotipo |  |
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HCPL-7723/0723
50 MBd 2 ns PWD High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either 8-pin DIP or SO‑8 package style respec-
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize
the latest CMOS IC technology to achieve outstanding
speed performance of minimum 50 MBd data rate and
2 ns maximum pulse width distortion.
Basic building blocks of HCPL-7723/0723 are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver
IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
Functional Diagram
**VDD1 1
8 VDD2**
Features
• +5 V CMOS compatibility
• High speed: 50 MBd min.
• 2 ns max. pulse width distortion
• 22 ns max. prop. delay
• 16 ns max. prop. delay skew
• 10 kV/µs min. common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals:
UL recognized
– 5000 Vrms for 1 min. per UL1577 for HCPL-7723 for
option 020
– 3750 Vrms for 1 min. per UL1577 for HCPL-0723
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– Viorm = 630 Vpeak for HCPL-7723 option 060
– Viorm = 567 Vpeak for HCPL-0723 option 060
VI 2
NC* 3
GND1 4
LED1
SHIELD
7 NC*
IO
6 VO
5 GND2
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
Applications
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
• Multiplexed data transmission
• High speed digital input/output
• Computer peripheral interface
• Microprocessor system interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.
1 page  
Regulatory Information
The HCPL-7723/0723 have been approved by the following organizations:
UL
Recognized under UL1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5, File CA88324.
IEC/EN/DIN EN 60747-5-5
Approved with Maximum Working Insulation Voltage:
Viorm = 567 Vpeak for HCPL-0723,
Viorm = 630 Vpeak for HCPL-7723
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Insulation and Safety Related Specifications
Value
Parameter
Symbol 7723 0723 Units Conditions
Minimum External Air Gap
L(I01) 7.1 4.9 mm
(Clearance)
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External Tracking
L(I02) 7.4 4.8 mm
(Creepage)
Measured from input terminals to output
terminals, shortest distance path along body.
Minimum Internal Plastic Gap
0.08 0.08 mm
Insulation thickness between emitter and
(Internal Clearance)
detector; also known as distance through
insulation.
Tracking Resistance
(Comparative Tracking Index)
CTI ≥ 175 ≥ 175 Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group
IIIa IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
5
5 Page 
Application Information
Bypassing and PC Board Layout
The HCPL-7723/0723 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-7723/0723 use high-speed CMOS IC technol-
ogy allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 8 illustrates the recommended
printed circuit board layout for the HCPL-7723/0723.
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 9. The propagation delay from low
to high (tPLH) is the amount of time required for an input
signal to propagate to the output, causing the output to
change from low to high. Similarly, the propagation delay
from high to low (tPHL) is the amount of time required for
the input signal to propagate to the output, causing the
output to change from high to low.
VDD1
VI
C1
1
2
NC 3
GND1
4
8
7 NC
C2
VDD2
6 VO
5 GND2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Functional diagram.
VDD1
VI
GND1
C1
Figure 8. Recommended printed circuit board layout.
VDD2
C2
VO
GND2
C1, C2 = 0.01 µF TO 0.1 µF
INPUT
VI
OUTPUT
VO
10%
tPLH
90%
tPHL
50%
90%
10%
5 V CMOS
0V
VOH
2.5 V CMOS
VOL
Figure 9. Timing diagram to illustrate propagation delay, tplh and tphl.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HCPL-0723.PDF ] | |
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