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PDF FDMC7660DC Data sheet ( Hoja de datos )

Número de pieza FDMC7660DC
Descripción N-Channel Dual Cool 33 PowerTrenc MOSFET
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FDMC7660DC Hoja de datos, Descripción, Manual

July 2015
FDMC7660DC
N-Channel Dual CoolTM 33 PowerTrench® MOSFET
30 V, 40 A, 2.2 mΩ
Features
General Description
„ Dual CoolTM Top Side Cooling PQFN package
„ Max rDS(on) = 2.2 mΩ at VGS = 10 V, ID = 22 A
„ Max rDS(on) = 3.3 mΩ at VGS = 4.5 V, ID = 18 A
„ High performance technology for extremely low rDS(on)
„ SyncFET Schottky Body Diode
„ RoHS Compliant
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process.
Advancements in both silicon and Dual CoolTM package
technologies have been combined to offer the lowest rDS(on)
while maintaining excellent switching performance by extremely
low Junction-to-Ambient thermal resistance.
Applications
„ Synchronous Rectifier for DC/DC Converters
„ Telecom Secondary Side Rectification
„ High End Server/Workstation
Pin 1
G
S
S
S
D5
D6
4G
3S
D
D
D
D
Top
Dual CoolTM 33
Bottom
D7
D8
2S
1S
MOSFET Maximum Ratings TA= 25°C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
dv/dt
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
-Pulsed
TC = 25 °C
TC = 25 °C
TA = 25 °C
Single Pulse Avalanche Energy
Peak Diode Recovery dv/dt
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
(Note 4)
(Note 1a)
(Note 3)
(Note 5)
(Note 1a)
Ratings
30
±20
40
150
30
200
220
1.0
78
3.0
-55 to + 150
Units
V
V
A
mJ
V/ns
W
°C
RθJC
RθJC
RθJA
RθJA
RθJA
RθJA
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Top Source)
(Bottom Drain)
(Note 1a)
(Note 1b)
(Note 1i)
(Note 1j)
(Note 1k)
4.3
1.6
42
105
17
26
12
°C/W
Device Marking
7660
Device
FDMC7660DC
©2011 Fairchild Semiconductor Corporation
FDMC7660DC Rev.1.3
Package
Dual CoolTM 33
1
Reel Size
13’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com

1 page




FDMC7660DC pdf
Typical Characteristics TJ = 25°C unless otherwise noted
10
ID = 22 A
8
6
4
VDD = 10 V
VDD = 15 V
VDD = 20 V
2
0
0 10 20 30 40 50 60
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
6000
1000
Ciss
Coss
100 f = 1 MHz
VGS = 0 V
50
0.1
1
Crss
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
30
Figure8. CapacitancevsDrain
to Source Voltage
30 160
VGS = 10 V
RθJC = 1.6 oC/W
TJ = 25 oC
120
10
TJ = 100 oC
VGS = 4.5 V
80
TJ = 125 oC
1
0.01
0.1 1
10
tAV, TIME IN AVALANCHE (ms)
Figure9. UnclampedInductive
Switching Capability
100 300
40
0
25
Limited by Package
50 75 100 125
TC, CASE TEMPERATURE (oC)
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
500
100
100 us
10 1 ms
1
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
0.1 TJ = MAX RATED
RθJA = 105 oC/W
TA = 25 oC
0.01
0.01 0.1
1
10
VDS, DRAIN to SOURCE VOLTAGE (V)
10 ms
100 ms
1s
10s
DC
100
Figure 11. Forward Bias Safe
Operating Area
104
SINGLE PULSE
103 RθJA = 105 oC/W
TA = 25 oC
102
10
1
0.2
10-4
10-3 10-2 10-1
1
t, PULSE WIDTH (sec)
10
100 1000
Figure 12. Single Pulse Maximum
Power Dissipation
©2011 Fairchild Semiconductor Corporation
FDMC7660DC Rev.1.3
5
www.fairchildsemi.com

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