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PDF MRF24XA Data sheet ( Hoja de datos )

Número de pieza MRF24XA
Descripción 2.4 GHz ISM-Band IEEE 802.15.4 RF Transceiver
Fabricantes Microchip 
Logotipo Microchip Logotipo



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No Preview Available ! MRF24XA Hoja de datos, Descripción, Manual

MRF24XA
Low-Power, 2.4 GHz ISM-Band IEEE 802.15.4™ RF
Transceiver with Extended Proprietary Features
Features
• IEEE 802.15.4™-2003 and IEEE 802.15.4-2006
Standard Compliant RF transceiver
• Multiple air-data-rates:
- 250 kbps (IEEE 802.15.4)
- 125, 500, 1000, 2000 kbps, co-existence with
standard networks
• Configurable TX output power: -19 to 1 dBm
• Frame header duration scales with the selected
data rate
• On-the-fly, per frame air-data-rate detection
(link-by-link independent air-data-rates)
• Inferred destination addressing (to further save on
framing overheads; optional)
Full-Featured MCU Support
• Hardware frame parser
• Hardware CSMA-CA controller, automatic
Acknowledgment (ACK) and Frame Check
Sequence (FCS)
• Supports all Clear Channel Assessment (CCA)
modes
• Reports ED, RSSI, LQI, and CFO
• Channel Agility with acknowledgments
• Two independent 128 byte frame buffers
• Streaming mode to maximize throughput
• Automatic packet retransmit capability
• Hardware Security Engine (AES-128) and
configurable Encryption/Decryption mode
Low-Power
• Extreme minimization of radio ON time
- Highest channel-admissible data rate used
- 20%-70% overall reduction through framing
• 2 Mbps frames can reduce radio ON time by a factor
of 4 to 8 with respect to 250 kbps frames
• 27.5 mA TX current (typical at 0 dBm)
• 13.5 mA RX current in RX Listen Power-Saving mode
• 15.5-16.5 mA RX current in RX Packet Demodulation
mode (data rate and device Configuration dependent)
• Deep Sleep, Sleep, Crystal ON, and RX Listen
Power-Saving modes
• Memory retention in Deep Sleep mode (<40 nA typi-
cal)
• Automated functions minimize MCU ON time
General
• Low external component count
• Best-in-class battery life preservation
• Supply range: 1.5V to 3.6V
• Compact 32-pin 5x5 mm2 QFN package
• Temperature range: -40oC to +85oC
• Certified turnkey-ready solutions available
Applications
• IEEE 802.15.4/ZigBee® systems (RF4CE and
MiWiTM network)
• Industrial monitoring and control
• IEEE 1588 precise timing protocol networks
• Automatic meter reading
• Home building automation
• Low-power wireless sensor networks
• Consumer electronics, voice and audio
2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 1

1 page




MRF24XA pdf
1.0 DEVICE OVERVIEW
MRF24XA is an IEEE 802.15.4™ Standard compliant
2.4 GHz RF transceiver with feature extensions.
MRF24XA integrates the PHY and MAC functionality in
a single-chip solution. MRF24XA implements a low-
cost, low-power, high data rate (125 kbps to 2 Mbps)
Wireless Personal Area Network (WPAN) device. All
the data rates contains the same spectral shape
requiring identical bandwidth. At 125 kbps data rate
Direct Sequence Spread Spectrum (DSSS) is
combined with error correction and coding for
maximum range and robustness against interference.
The 2 Mbps data rate is used to minimize radio ON
time, therefore extending battery life. Figure 1-1
illustrates a simplified block diagram of a MRF24XA
wireless node. MRF24XA interfaces to many popular
Microchip PIC® microcontrollers through a 4-wire serial
SPI interface, interrupt, GPIO, and RESET pins.
MRF24XA can also handle external Power Amplifier
(PA) and Low Noise Amplifier (LNA).
MRF24XA
MRF24XA provides hardware support for:
• Energy detection
• Carrier sense
• Four CCA modes
• CSMA-CA algorithm
• Automatic packet retransmission
• Automatic acknowledgement
• Independent transmit and receive buffers
• Security engine supports encryption and
decryption for MAC sublayer and upper layer
• Inferred destination addressing
• Channel agility with ACKs
• Battery monitoring
These features reduce the processing load, allowing
the use of low-cost 8-bit microcontrollers.
MRF24XA is compatible with Microchip’s ZigBee®,
MiWi™ and MiWi P2P software stacks. Each software
stack is available as a free download, including source
code, from the Microchip web site:
http://www.microchip.com/wireless.
FIGURE 1-1:
Antenna
MRF24XA WIRELESS NODE BLOCK DIAGRAM
MRF24XA
RFOUTP
RFOUTN
RFINP
RFINN
PHY
MAC
Interface
CS
SDI
SDO
SCK
Power
Management
INT
RESET
PIC® MCU
IO
SDO
SDI
SCK
INTX
IO
16 MHz
crystal
2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 5

5 Page





MRF24XA arduino
2.4.3 RESET (RESET) PIN
An external Hardware Reset is performed by asserting
the RESET pin 18 low. If the RESET pin is deasserted,
MRF24XA starts the internal Calibration process. RDYIF
interrupt is set when the device is ready to use. The
RESET pin contains an internal weak pull-up resistor.
2.4.4
INTERRUPT (INT) PIN
The Interrupt (INT) pin 13 provides an interrupt signal
to the host MCU from MRF24XA where the signal is
active-low polarity. Interrupt sources must be enabled
and unmasked before the INT pin becomes active.
Refer to Section 3.2 “Interrupts” for the functional
description of interrupts.
2.4.5
GENERAL PURPOSE INPUT/
OUTPUT (GPIO) PINS
Three GPIO pins are configured individually for control or
monitoring purposes. The TRISGPIOx bits in the GPIO
register (0x0D) configures the input or output selection.
GPIO data is read or written through the GPIO bits of
GPIO register. The GPIO interrupt polarity is selected
through GPIOxP bits in the STGPIO (0x0E) register.
GPIO lines in Input mode are used in Schmitt Trigger
Input mode. STENGPIOx bits of STGPIO register
enables Schmitt Triggers. GPIOs are also used to
monitor the internal blocks. The GPIOMODE bits <3:0>
of the PINCON (0x0C) register selects these
monitoring functions.
MRF24XA
2.4.6
SERIAL PERIPHERAL INTERFACE
(SPI) PORT PINS
MRF24XA communicates with a host MCU through a
4-wire SPI port as a slave device. MRF24XA supports
SPI mode 0,0, which requires that SCK idles in a low
state. The CS pin must be held low while communicat-
ing with MRF24XA. Figure 2-3 illustrates timing for a
read and a write operation. MRF24XA receives the
data through the SDI pin and clocks in on the rising
edge of SCK. MRF24XA sends data through the SDO
pin and clocks out on the falling edge of SCK. The SDO
lines preserve its HiZ state in Deep Sleep mode.
2015 Microchip Technology Inc.
Preliminary
DS70005023C-page 11

11 Page







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