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PDF CDB43L42 Data sheet ( Hoja de datos )
| Número de pieza | CDB43L42 | |
| Descripción | Low Voltage/Stereo DAC With Headphone Amp | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS43L42
Low Voltage, Stereo DAC with Headphone Amp
Features
Description
l 1.8 to 3.3 Volt supply
l 24-Bit conversion / 96 kHz sample rate
l 96 dB dynamic range at 3 V supply
l -85 dB THD+N
l Low power consumption
l Digital volume control
— 96 dB attenuation, 1 dB step size
l Digital bass and treble boost
— Selectable corner frequencies
— Up to 12 dB boost in 1 dB increments
l Peak signal limiting to prevent clipping
l De-emphasis for 32 kHz, 44.1 kHz, and 48 kHz
l Headphone amplifier
— up to 25 mWrms power output into 16 Ω load*
— 25 dB analog attenuation and mute
— Zero crossing click free level transitions
l ATAPI mixing functions
l 24-Pin TSSOP package
* 1 kHz sine wave at 3.3V supply
The CS43L42 is a complete stereo digital-to-analog out-
put system including interpolation, 1-bit D/A conversion,
analog filtering, volume control, line level outputs, and a
headphone amplifier, in a 24-pin TSSOP package.
The CS43L42 is based on delta-sigma modulation,
where the modulator output controls the reference volt-
age input to an ultra-linear analog low-pass filter. This
architecture allows infinite adjustment of the sample rate
between 2 kHz and 100 kHz simply by changing the
master clock frequency.
The CS43L42 contains on-chip digital bass and treble
boost, peak signal limiting, and de-emphasis. The
CS43L42 operates from a +1.8 V to +3.3 V supply and
consumes only 16 mW of power with a 1.8 V supply with
the line amplifier powered-down. These features are
ideal for portable CD, MP3 and MD players and other
portable playback systems that require extremely low
power consumption.
ORDERING INFORMATION
CS43L42-KZ -10 to 70 °C
CDB43L42
24-pin TSSOP
Evaluation Board
RST
VA
VL
LRCK
SCLK/DEM1
SDATA
SCL/CCLK/DIF1 SDA/CDIN/DIF0 AD0/CS/DEM0
MUTEC
Control Port
External
Mute Control
Digital
Volume
Control
Bass/Treble
Boost
Limiting
∆Σ
DAC
∆Σ
DAC
Analog
Filter
Analog
Filter
VQ_HP
VA_HP
Analog
Volume
Control
Analog
Volume
Control
HP_A
HP_B
AOUTA
AOUTB
GND
MCLK
FILT+ REF_GND
VQ_LINE VA_LINE
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
APR ‘00
DS481PP1
1
1 page  
CS43L42
1. CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25° C; Logic "1" = VL = 1.8 V; Logic "0" = GND = 0 V;
Full-Scale Output Sine Wave, 997 Hz; MCLK = 12.288 MHz; Measurement Bandwidth 10 Hz to 20 kHz, unless oth-
erwise specified; Fs for Base-rate Mode = 48 kHz, SCLK = 3.072 MHz. Fs for High-Rate Mode = 96 kHz,
SCLK = 6.144 MHz. Test load RL = 10 kΩ, CL = 10 pF (see Figure 17) for line out, RL = 16 Ω, CL = 10 pF (see Fig-
ure 18) for headphone out).
Base-rate Mode
High-Rate Mode
Parameter
Symbol Min Typ Max Min Typ Max Unit
Line Output Dynamic Performance for VA = VA_LINE = 1.8 V
Dynamic Range
18 to 24-Bit
16-Bit
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
TBD
TBD
-
-
91
94
89
92
- TBD
- TBD
--
--
89
92
87
90
- dB
- dB
- dB
- dB
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-80 TBD -
-71 - -
-31 - -
-78 - -
-69 - -
-29 - -
-80 TBD dB
-69 - dB
-29 - dB
-78 - dB
-67 - dB
-27 - dB
Interchannel Isolation
(1 kHz)
- 100 - - 100 - dB
Headphone Output Dynamic Performance for VA = VA_HP = 1.8 V
Dynamic Range
18 to 24-Bit
16-Bit
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
TBD
TBD
-
-
88
91
86
89
- TBD
- TBD
--
--
88
91
86
89
- dB
- dB
- dB
- dB
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-82 TBD -
-68 - -
-28 - -
-80 - -
-66 - -
-26 - -
-85 TBD dB
-68 - dB
-28 - dB
-83 - dB
-66 - dB
-26 - dB
Interchannel Isolation
(1 kHz)
- 66 - - 66 - dB
Notes: 1. One-half LSB of triangular PDF dither is added to data.
DS481PP1
5
5 Page 
CS43L42
LRCK
t slrd
SCLK
SDATA
t sdlrs
t slrs
t sclkh
t sclkl
t sdh
LRCK
SDATA
*INTERNAL
SCLK
t sclkr
t sdlrs t sdh
t sclkw
Figure 1. External Serial Mode Input Timing
Figure 2. Internal Serial Mode Input Timing
*The SCLK pulses shown are internal to the CS43L42.
LRCK
MCLK
*INTERNAL SCLK
1N
2
N
SDATA
Figure 3. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L42.
N equals MCLK divided by SCLK
DS481PP1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CDB43L42.PDF ] | |
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