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Número de pieza | CY7C1263V18 | |
Descripción | 1.8V Synchronous Pipelined SRAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
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No Preview Available ! CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
36-Mbit QDR™-II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 300 MHz to 400 MHz clock for high bandwidth
■ 4-Word Burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 800 MHz) at 400 MHz
■ Read latency of 2.5 clock cycles
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate Port Selects for depth expansion
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ Available in x8, x9, x18, and x36 configurations
■ Full data coherency providing most current data
■ Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1261V18 – 4M x 8
CY7C1276V18 – 4M x 9
CY7C1263V18 – 2M x 18
CY7C1265V18 – 1M x 36
Functional Description
The CY7C1261V18, CY7C1276V18, CY7C1263V18, and
CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,
equipped with Quad Data Rate-II+ (QDR-II+) architecture.
QDR-II+ architecture consists of two separate ports to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR-II+ architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn around” the data bus required with common IO
devices. Each port is accessed through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II+ read
and write ports are completely independent of one another. To
maximize data throughput, both read and write ports are
equipped with Double Data Rate (DDR) interfaces. Each
address location is associated with four 8-bit words
(CY7C1261V18), 9-bit words (CY7C1276V18), 18-bit words
(CY7C1263V18), or 36-bit words (CY7C1265V18) that burst
sequentially into or out of the device. Because data can be trans-
ferred into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while simpli-
fying system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with Port Selects for each port.
Port selects enable each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
400 MHz
400
1330
375 MHz
375
1240
333 MHz
333
1120
300 MHz
300
1040
Unit
MHz
mA
Note
1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting
VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-06366 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 01, 2008
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1 page CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Pin Configurations (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1263V18 (2M x 18)
1 2 3 4 5 6 7 8 9 10 11
A CQ NC/144M A
WPS BWS1
K NC/288M RPS
A NC/72M CQ
B NC Q9 D9 A
NC
K
BWS0
A
NC NC Q8
C NC
NC D10 VSS
A
NC
A VSS NC Q7 D8
D NC
D11 Q10 VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M NC NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N NC D17 Q16 VSS
A
A
A VSS NC NC D1
P NC NC Q17 A
A QVLD A A NC D0 Q0
R TDO TCK
A
A
A NC A
A
A
TMS
TDI
CY7C1265V18 (1M x 36)
1 2 3 4 5 6 7 8 9 10 11
A
CQ NC/288M NC/72M WPS BWS2
K
BWS1 RPS
A NC/144M CQ
B Q27 Q18 D18 A BWS3 K BWS0 A
D17 Q17
Q8
C D27 Q28 D19 VSS A NC A VSS D16 Q7 D8
D
D28 D20 Q19 VSS
VSS
VSS
VSS
VSS
Q16 D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33 Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N D34 D26 Q25 VSS
A
A
A VSS Q10 D9 D1
P Q35 D35 Q26 A
A QVLD A A Q9 D0 Q0
R TDO TCK
A
A
A NC A
A
A
TMS
TDI
Document Number: 001-06366 Rev. *E
Page 5 of 29
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5 Page CY7C1261V18, CY7C1276V18
CY7C1263V18, CY7C1265V18
Write Cycle Descriptions
The write cycle descriptions table for CY7C1261V18 and CY7C1263V18 follows.[2, 10]
BWS0/ BWS1/ K
NWS0 NWS1
K
Comments
L L L–H – During the data portion of a write sequence:
CY7C1261V18 − both nibbles (D[7:0]) are written into the device.
CY7C1263V18 − both bytes (D[17:0]) are written into the device.
L L – L-H During the data portion of a write sequence:
CY7C1261V18 − both nibbles (D[7:0]) are written into the device.
CY7C1263V18 − both bytes (D[17:0]) are written into the device.
L H L–H – During the data portion of a write sequence:
CY7C1261V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1263V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L H – L–H During the data portion of a write sequence:
CY7C1261V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1263V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
H L L–H – During the data portion of a write sequence:
CY7C1261V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1263V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H L – L–H During the data portion of a write sequence:
CY7C1261V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1263V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H H L–H – No data is written into the devices during this portion of a write operation.
H H – L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle descriptions table for CY7C1276V18 follows.[2, 10]
BWS0
L
L
H
K
L–H
–
L–H
K Comments
– During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
– No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Note
10. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions
of a write cycle, as long as the setup and hold requirements are met.
Document Number: 001-06366 Rev. *E
Page 11 of 29
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11 Page |
Páginas | Total 29 Páginas | |
PDF Descargar | [ Datasheet CY7C1263V18.PDF ] |
Número de pieza | Descripción | Fabricantes |
CY7C1263V18 | 1.8V Synchronous Pipelined SRAM | Cypress Semiconductor |
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