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PDF CY7C1018V33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1018V33 | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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019V 33
CY7C1018V33
CY7C1019V33
Features
• High speed
— tAA = 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
Functional Description
The CY7C1018V33/CY7C1019V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
Logic Block Diagram
128K x 8 Static RAM
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018V33 is available in a standard 300-mil-wide
SOJ and CY7C1019V33 is available in a standard
400-mil-wide package. The CY7C1018V33 and
CY7C1019V33 are functionally equivalent in all other re-
spects.
Pin Configurations
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1019V33–1
SOJ
Top View
A0
A1
A2
A3
CE
I/O0
I/O1
VCC
V SS
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 A16
31 A15
30 A14
29 A13
28 OE
27 I/O7
26 I/O6
25 VSS
24 VCC
23 I/O5
22 I/O4
21 A12
20 A11
19 A10
18 A9
17 A8
1019V33–2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
7C1019V33-10
7C1018V33-12
7C1019V33-12
7C1018V33-15
7C1019V33-15
10 12 15
175 160 145
555
L−
0.5 0.5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05150 Rev. **
Revised September 18, 2001
1 page  
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12, 13]
ADDRESS
CE
tSA
WE
DATA I/O
tWC
tSCE
tSCE
tAW
tPWE
tSD
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
CY7C1018V33
CY7C1019V33
tHA
tHD
1019V33–8
ADDRESS
CE
WE
tWC
tSCE
tAW
tSA tPWE
OE
DATA I/O
NOTE 14
tHZOE
tSD
DATAIN VALID
Notes:
12. Data I/O is high impedance if OE = VIH.
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14. During this period the I/Os are in the output state and input signals should not be applied.
tHA
tHD
1019V33–98
Document #: 38-05150 Rev. **
Page 5 of 8
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CY7C1018V33.PDF ] | |
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