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PDF S25FL128P Data sheet ( Hoja de datos )

Número de pieza S25FL128P
Descripción 128-Mb 3.0 V Flash Memory
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! S25FL128P Hoja de datos, Descripción, Manual

S25FL128P
128-Mb 3.0 V Flash Memory
This product is not recommended for new and current designs. For new and current designs, S25FL128S supersedes
S25FL128P. This is the factory-recommended migration path. Please refer to the S25FL128S data sheet for
specifications and ordering information.
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7V to 3.6V read and program operations
Memory Architecture
– 128Mb uniform 256 KB sector product
– 128Mb uniform 64 KB sector product
Program
– Page Program (up to 256 bytes) in 1.5 ms (typical)
– Faster program time in Accelerated Programming mode
(8.5 V–9.5 V on #WP/ACC) in 1.2 ms (typical)
Erase
– 2 s typical 256 KB sector erase time
– 0.5 s typical 64 KB sector erase time
– 128 s typical bulk erase time
– Sector erase (SE) command (D8h) for 256 KB sectors; (20h or
D8h) for 64KB sectors
– Bulk erase command (C7h) for 256 KB sectors; (60h or C7h) for
64KB sectors
Cycling Endurance
– 100,000 cycles per sector typical
Data Retention
– 20 years typical
Device ID
– RDID (9Fh), READ_ID (90h) and RES (ABh) commands to read
manufacturer and device ID information
– RES command one-byte electronic signature for backward
compatibility
Process Technology
– Manufactured on 0.09 µm MirrorBit® process technology
Package Option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-Contact WSON Package (6 x 8 mm)
Performance Characteristics
Speed
– 104 MHz clock rate (maximum)
Power Saving Standby Mode
– Standby Mode 200 µA (max)
– Deep Power Down Mode 3 µA (typical)
Memory Protection Features
Memory Protection
– WP#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– 256 KB uniform sector product:
Status Register Block Protection bits (BP2, BP1, BP0) in status
register configure parts of memory as read-only.
– 64KB uniform sector product:
Status Register Block Protection bits (BP3, BP2, BP1, BP0) in
status register configure parts of memory as read-only
Software Features
– SPI Bus Compatible Serial Interface
Hardware Features
x8 Parallel Programming Mode (for 16-pin SO package only)
General Description
The S25FL128P is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device consists of 64 sectors of
256 KB memory, or 256 sectors of 64 KB memory.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be
programmed in-system with the standard system 3.0 volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase
and Bulk Erase commands.
Each device requires only a 3.0 volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and
regulated voltages are provided for the program operations. This device requires a high voltage supply to WP#/ACC pin for the
Accelerated Programming mode.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00646 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 18, 2015

1 page




S25FL128P pdf
S25FL128P
3. Input/Output Descriptions
Signal Name
SO (Signal Data Output)
PO[7–0] (Parallel Data Input/Output)
I/O
Output
Input/Output
SI (Serial Data Input)
Input
SCK (Serial Clock)
Input
CS# (Chip Select)
Input
HOLD# (Hold)
WP#/ACC
(Write Protect/Accelerated Programming)
VCC
GND
Input
Input
Input
Input
Description
Transfers data serially out of the device on the falling edge of SCK.
Transfers parallel data into the device on the rising edge of SCK or out of the device on
the falling edge of SCK.
Transfers data serially into the device. Device latches commands, addresses, and
program data on SI on the rising edge of SCK.
Provides serial interface timing. Latches commands, addresses, and data on SI on rising
edge of SCK. Triggers output on SO after the falling edge of SCK.
Places device in active power mode when driven low. Deselects device and places SO
at high impedance when high. After power-up, device requires a falling edge on CS#
before any command is written. Device is in standby mode when a program, erase, or
Write Status Register operation is not in progress.
Pauses any serial communication with the device without deselecting it. When driven
low, SO is at high impedance, and all input at SI and SCK are ignored. Requires that
CS# also be driven low.
When driven low, prevents any program or erase command from altering the data in the
protected memory area specified by Status Register bits (BP bits). If the system asserts
VHH on this pin, accelerated programming operation is provided.
Supply Voltage
Ground
4. Logic Symbol
VCC
SI
SCK
CS#
WP#/ACC
HOLD#
GND
SO
PO[7-0] (For 16-pin SO package)
Document Number: 002-00646 Rev. *L
Page 6 of 45

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S25FL128P arduino
Table 8.2 S25FL128P Sector Address Table (Uniform 256 KB sector)
Sector
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Address Range
FC0000h
FFFFFFh
F80000h
FBFFFFh
F40000h
F7FFFFh
F00000h
F3FFFFh
EC0000h
EFFFFFh
E80000h
EBFFFFh
E40000h
E7FFFFh
E00000h
E3FFFFh
DC0000h
DFFFFFh
D80000h
DBFFFFh
D40000h
D7FFFFh
D00000h
D3FFFFh
CC0000h
CFFFFFh
C80000h
CBFFFFh
C40000h
C7FFFFh
C00000h
C3FFFFh
BC0000h
BFFFFFh
B80000h
BBFFFFh
B40000h
B7FFFFh
B00000h
B3FFFFh
AC0000h
AFFFFFh
A80000h
ABFFFFh
A40000h
A7FFFFh
A00000h
A3FFFFh
9C0000h
9FFFFFh
980000h
9BFFFFh
940000h
97FFFFh
900000h
93FFFFh
8C0000h
8FFFFFh
880000h
8BFFFFh
840000h
87FFFFh
800000h
83FFFFh
Sector
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S25FL128P
Address Range
7C0000h
7FFFFFh
780000h
7BFFFFh
740000h
77FFFFh
700000h
73FFFFh
6C0000h
6FFFFFh
680000h
6BFFFFh
640000h
67FFFFh
600000h
63FFFFh
5C0000h
5FFFFFh
580000h
5BFFFFh
540000h
57FFFFh
500000h
53FFFFh
4C0000h
4FFFFFh
480000h
4BFFFFh
440000h
47FFFFh
400000h
43FFFFh
3C0000h
3FFFFFh
380000h
3BFFFFh
340000h
37FFFFh
300000h
33FFFFh
2C0000h
2FFFFFh
280000h
2BFFFFh
240000h
27FFFFh
200000h
23FFFFh
1C0000h
1FFFFFh
180000h
1BFFFFh
140000h
17FFFFh
100000h
13FFFFh
0C0000h
0FFFFFh
080000h
0BFFFFh
040000h
07FFFFh
000000h
03FFFFh
Document Number: 002-00646 Rev. *L
Page 12 of 45

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