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PDF S25FL132K Data sheet ( Hoja de datos )

Número de pieza S25FL132K
Descripción 3.0V SPI Flash Memory
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! S25FL132K Hoja de datos, Descripción, Manual

S25FL116K, S25FL132K, S25FL164K
16 Mbit (2 Mbyte), 32 Mbit (4 Mbyte),
64 Mbit (8 Mbyte) 3.0V SPI Flash Memory
Features
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Command subset and footprint compatible with S25FL-K
Read
– Normal Read (Serial):
– 50 MHz clock rate (40 °C to +85 °C/105 °C)
– 45 MHz clock rate (40 °C to +125 °C)
– Fast Read (Serial):
– 108 MHz clock rate (40 °C to +85 °C/105 °C)
– 97 MHz clock rate (40 °C to +125 °C)
– Dual Read:
– 108 MHz clock rate (40 °C to +85 °C/105 °C)
– 97 MHz clock rate (40 °C to +125 °C)
– Quad Read:
– 108 MHz clock rate (40 °C to +85 °C/105 °C)
– 97 MHz clock rate for S25FL164K (40 °C to +125 °C)
– 54 MB/s maximum continuous data transfer rate
(40 °C to +85 °C/105 °C)
– Efficient Execute-In-Place (XIP)
– Continuous and wrapped read modes
– Serial Flash Discoverable Parameters (SFDP)
Program
– Serial-input Page Program (up to 256 bytes)
– Program Suspend and Resume
Erase
– Uniform sector erase (4 kB)
– Uniform block erase (64 kB)
– Chip erase
– Erase Suspend and Resume
Cycling Endurance
– 100K Program-Erase cycles on any sector
Data Retention
– 20-year data retention
Security
– Three 256-byte Security Registers with OTP protection
– Low supply voltage protection of the entire memory
– Pointer-based security protection feature (S25FL132K and
S25FL164K)
– Top / Bottom relative Block Protection Range, 4 kB to all of
memory
– 8-Byte Unique ID for each device
– Non-volatile Status Register bits control protection modes
– Software command protection
– Hardware input signal protection
– Lock-Down until power cycle protection
– OTP protection of security registers
90 nm Floating Gate Technology
Single Supply Voltage
– 2.7 V to 3.6 V (Industrial, Industrial Plus, and Extended
temperature range)
– 2.6 V to 3.6 V (Extended temperature range)
Temperature Ranges
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Extended (40 °C to +125 °C)
– Industrial, GT Grade, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Industrial Plus, GT Grade, AEC-Q100 Grade 2(40 °C to +105 °C)
– Extended, GT Grade, AEC-Q100 Grade 1 (40 °C to +125 °C)
Package Options
– S25FL116K
– 8-lead SOIC (150 mil) – SOA008
– 8-lead SOIC (208 mil) – SOC008
– 8-contact WSON 5 mm x 6 mm – WND008
– 24-ball BGA 6 mm 8 mm – FAB024 and FAC024
– KGD / KGW
– S25FL132K
– 8-lead SOIC (150 mil) – SOA008
– 8-lead SOIC (208 mil) – SOC008
– 8-contact USON 4 mm 4 mm – UNF008
– 8-contact WSON 5 mm 6 mm – WND008
– 24-ball BGA 6 mm 8 mm – FAB024 and FAC024
– KGD / KGW
– S25FL164K
– 8-lead SOIC (208 mil) – SOC008
– 16-lead SOIC (300 mil) – SO3016
– 8-contact WSON 5 mm 6 mm – WND008
– 24-ball BGA 6 mm 8 mm – FAB024 and FAC024
– KGD / KGW
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00497 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 29, 2016

1 page




S25FL132K pdf
S25FL116K, S25FL132K, S25FL164K
1.1 Migration Notes
1.1.1
Features Comparison
The S25FL1-K is command set and footprint compatible with prior generation FL-K and FL-P families.
Table 1.1 FL Generations Comparison
Parameter
S25FL1-K
S25FL-K
Technology Node
90 nm
90 nm
Architecture
Floating Gate
Floating Gate
Release Date
In Production
In Production
Density
16 Mbit - 64 Mbit
4 Mbit - 128 Mbit
Bus Width
x1, x2, x4
x1, x2, x4
Supply Voltage
2.6V / 2.7V - 3.6V
2.7V - 3.6V
Normal Read Speed
6 MB/s (50 MHz)
5.4 MB/s (45 MHz for 125°C)
6 MB/s (50 MHz)
Fast Read Speed
13.5 MB/s (108 MHz)
12.12 MB/s (97 MHz for 125°C)
13 MB/s (104 MHz)
Dual Read Speed
27 MB/s (108 MHz)
24.25 MB/s (97 MHz for 125°C)
26 MB/s (104 MHz)
Quad Read Speed
54 MB/s (108 MHz at 85°C/105°C)
48.5 MB/s (97 MHz at 125°C)
52 MB/s (104 MHz)
Program Buffer Size
256B
256B
Page Programming Time
(typ.)
700 µs (256B)
700 µs (256B)
Program Suspend / Resume
Yes
Yes
Erase Sector Size
4 kB / 64 kB
4 kB / 32 kB / 64 kB
Parameter Sector Size
N/A
N/A
Sector Erase Time (typ.)
50 ms (4 kB), 500 ms (64 kB) 30 ms (4 kB), 150 ms (64 kB)
Erase Suspend / Resume
Yes
Yes
OTP Size
768B (3 x 256B)
768B (3 x 256B)
Operating Temperature
-40°C to +85°C / +105°C / +125°C
-40°C to +85°C
Notes:
1. S25FL-K family devices can erase 4-kB sectors in groups of 32 kB or 64 kB.
2. S25FL1-K family devices can erase 4-kB sectors in groups of 64 kB.
3. S25FL-P has either 64-kB or 256-kB uniform sectors depending on an ordering option.
4. Refer to individual data sheets for further details.
S25FL-P
90 nm
MirrorBit®
In Production
32 Mbit - 256 Mbit
x1, x2, x4
2.7V - 3.6V
5 MB/s (40 MHz)
13 MB/s (104 MHz)
20 MB/s (80 MHz)
40 MB/s (80 MHz)
256B
1500 µs (256B)
No
64 kB / 256 kB
4 kB
500 ms (64 kB)
No
506B
-40°C to +85°C / +105°C
1.1.2
Known Feature Differences from Prior Generations
1.1.2.1
Secure Silicon Region (OTP)
The size and format (address map) of the One Time Program area is the same for the S25FL1-K and the S25FL-K but different for
the S25FL-P.
Document Number: 002-00497 Rev. *E
Page 5 of 90

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S25FL132K arduino
S25FL116K, S25FL132K, S25FL164K
2.13 Do Not Use (DNU)
A device internal signal may be connected to the package connector. The connection may be used by Cypress for test or other
purposes and is not intended for connection to any host system signal. Any DNU signal related function will be inactive when the
signal is at VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to VSS.
Do not use these connections for PCB signal routing channels. Do not connect any host system signal to these connections.
2.14 Block Diagrams
Figure 2.2 Bus Master and Memory Devices on the SPI Bus – Single Bit Data Path
HOLD#
WP#
SI
SO
SCK
HOLD#
WP#
SI
SO
SCK
CS2#
CS1# CS1#
CS2#
SPI
Bus Master
SPI
Flash
SPI
Flash
Figure 2.3 Bus Master and Memory Devices on the SPI Bus – Dual Bit Data Path
HOLD#
WP#
IO1
IO0
SCK
CS2#
CS1#
CS1#
HOLD#
WP#
IO1
IO0
SCK
CS2#
SPI
Bus Master
SPI
Flash
SPI
Flash
Figure 2.4 Bus Master and Memory Devices on the SPI Bus – Quad Bit Data Path
IO3
IO2
IO1
IO0
SCK
IO3
IO2
IO1
IO0
SCK
CS2#
CS1# CS1#
CS2#
SPI
Bus Master
SPI
Flash
SPI
Flash
Document Number: 002-00497 Rev. *E
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