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PDF KAI-11002 Data sheet ( Hoja de datos )

Número de pieza KAI-11002
Descripción Interline CCD Image Sensor
Fabricantes ON Semiconductor 
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KAI-11002
4008 (H) x 2672 (V) Interline
CCD Image Sensor
Description
The KAI−11002 Image Sensor is a high-performance 11-million
pixel sensor designed for professional digital still camera applications.
The 9.0 mm square pixels with microlenses provide high sensitivity
and the large full well capacity results in high dynamic range. The two
high-speed outputs and binning capabilities allow for 1−3 frames per
second (fps) video rate for the progressively scanned images.
The vertical overflow drain structure provides anti-blooming
protection and enables electronic shuttering for precise exposure
control. Other features include low dark current, negligible lag and
low smear.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
Interline CCD, Progressive Scan
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
4072 (H) × 2720 (V) = 11.1 M
4033 (H) × 2688 (V) = 10.8 M
4008 (H) × 2672 (V) = 10.7 M
Number of Outputs
Pixel Size
Active Image Size
1 or 2
9.0 mm (H) × 9.0 mm (V)
37.25 mm (H) × 25.70 mm (V),
43.3 mm (Diagonal),
35 mm Optical Format
Aspect Ratio
Saturation Signal
Quantum Efficiency
KAI−11002−ABA
KAI−11002−CBA (RGB)
KAI−11002−FBA (RGB)
Output Sensitivity
Total Noise
3:2
60,000 e
50%
32%, 34%, 40%
35%, 38%, 40%
13 mV/e
30 e
Dark Current
Dark Current Doubling
Temperature
< 50 mV/s
7°C
Dynamic Range
66 dB
Charge Transfer Efficiency
Blooming Suppression
> 0.99999
> 1000X
Smear
Image Lag
< −80 dB
< 10 e
Maximum Data Rate
28 MHz
Package
40-pin, CERDIP, 0.070Pin Spacing
Cover Glass
AR Coated
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
www.onsemi.com
Figure 1. KAI−11002 Interline CCD
Image Sensor
Features
High Resolution
High Sensitivity
High Dynamic Range
Low Noise Architecture
High Frame Rate
Binning Capability for Higher Frame Rate
Electronic Shutter
Applications
Industrial Inspection
Aerial Photography
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 4
1
Publication Order Number:
KAI−11002/D

1 page




KAI-11002 pdf
KAI−11002
Vertical to Horizontal Transfer
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Direction of
Horizontal
Charge Transfer
Figure 4. Vertical to Horizontal Transfer Architecture
When the V1 and V2 timing inputs are pulsed, charge in
every pixel of the VCCD is shifted one row towards the
HCCD. The last row next to the HCCD is shifted into the
HCCD. When the VCCD is shifted, the timing signals to the
HCCD must be stopped. H1 must be stopped in the high state
and H2 must be stopped in the low state. The HCCD
clocking may begin tHD ms after the falling edge of the V1
and V2 pulse.
Charge is transferred from the last vertical CCD phase into
the H1S horizontal CCD phase. Refer to Figure 26 for an
example of timing that accomplishes the vertical to
horizontal transfer of charge.
If the fast line dump is held at the high level (FDH) during
a vertical to horizontal transfer, then the entire line is
removed and not transferred into the horizontal register.
www.onsemi.com
5

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KAI-11002 arduino
KAI−11002
Table 6. PERFORMANCE SPECIFICATIONS (continued)
Description
Symbol
Min.
Nom.
Max.
KAI−11002−ABA CONFIGURATION
Peak Quantum Efficiency
QEMAX
45
50 N/A
Peak Quantum Efficiency Wavelength
lQE
N/A
500
N/A
KAI−11002−FBA CONFIGURATION GEN2 COLOR
Peak Quantum Efficiency
Red
Green
Blue
QEMAX
35 N/A
38 N/A
40 N/A
Peak Quantum Efficiency Wavelength
Red
Green
Blue
lQE
610 N/A
530 N/A
460 N/A
KAI−11002−CBA CONFIGURATION GEN1 COLOR (Note 7)
Peak Quantum Efficiency
Red
Green
Blue
QEMAX
32 N/A
34 N/A
40 N/A
Peak Quantum Efficiency Wavelength
Red
Green
Blue
lQE
620 N/A
540 N/A
460 N/A
NOTE: N/A = Not Applicable.
1. Per color.
2. Value is over the range of 10% to 90% of photodiode saturation.
3. Value is for the sensor operated without binning.
4. Includes system electronics noise, dark pattern noise and dark current shot noise at 30 MHz.
5. Uses 20LOG (PNe / ne−T).
6. Last stage only, CLOAD = 10 pF. Then f−3dB = (1 / (2n ROUT CLOAD)).
7. This color filter set configuration (Gen1) is not recommended for new designs.
Unit
%
nm
%
nm
%
nm
Sample
Plan
Temperature
Tested at
(5C)
Design
Design
Design
Design
Design
www.onsemi.com
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