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PDF DP7401 Data sheet ( Hoja de datos )
| Número de pieza | DP7401 | |
| Descripción | Quad Digital Potentiometer | |
| Fabricantes | COPAL ELECTRONICS | |
| Logotipo |  |
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Quad Digital Potentiometers
(DP) with 64 Taps and SPI Interface
DP7401
FEATURES
Four linear taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5k, 10k, 50k or
100k
Potentiometer control and memory access via
SPI interface: Mode (0, 0) and (1, 1)
Low wiper resistance, typically 80
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Industrial temperature range
For Ordering Information details, see page 14.
DESCRIPTION
The DP7401 is four Digital Potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of 63 resistive elements connected between
two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The DP7401 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC Package (W)
TSSOP Package (Y)
VCC
RL0
RH0
RW0
CS
WP
SI
A1
RL1
RH1
RW1
GND
1 24
2 23
3 22
4 21
5 20
6 DP 19
7 7401 18
8 17
9 16
10 15
11 14
12 13
NC SI
RL3
RH3
A1
RL1
RW3 RH1
A0 RW1
SO GND
HOLD NC
SCK RW2
RL2 RH2
RH2 RL2
RW2 SCK
NC HOLD
1 24
2 23
3 22
4 21
5 20
6 DP 19
7 7401 18
8 17
9 16
10 15
11 14
12 13
WP
CS
RW0
RH0
RL0
VCC
NC
RL3
RH3
RW3
A0
SO
FUNCTIONAL DIAGRAM
CS
SCK
SI
SO
WP
A0
A1
RH0
RH1
RH2
RH3
SPI BUS
INTERFACE
WIPER CONTROL
REGISTERS
CONTROL LOGIC
NONVOLATILE
DATA
REGISTERS
RW0
RW1
RW2
RW3
RL0 RL1 RL2
RL3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2012 Rev. H
1 page  
DP7401
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
ICC
ISB
ILI
ILO
VIL
VIH
VOL1
Parameter
Power Supply Current
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = 3.0V)
Test Conditions
fSCL = 2MHz, SO = Open
Inputs = GND
VIN = GND or VCC, SO = Open
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3 mA
Min Max Units
1 mA
-1
VCC x 0.7
1
10
10
VCC x 0.3
VCC + 1.0
0.4
µA
µA
µA
V
V
V
PIN Capacitance (1)
Available over recommended operating range from TA = 25ºC, f = 1.0MHz, VCC = 5V (unless otherwise noted).
Symbol Test
Conditions
Max. Units
COUT
CIN
Output Capacitance (SO)
Input Capacitance (¯C¯S¯, SCK, SI, ¯W¯P¯, ¯H¯O¯L¯D¯)
VOUT = 0V
VIN = 0V
8 pF
6 pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Test Conditions
Min
tSU Data Setup Time
tH Data Hold Time
tWH SCK High Time
tWL SCK Low Time
fSCK Clock Frequency
tLZ H¯¯O¯L¯D¯ to Output Low Z
tRI(1) Input Rise Time
tFI(1) Input Fall Time
tHD H¯¯O¯L¯D¯ Setup Time
tCD H¯¯O¯L¯D¯ Hold Time
tWC Write Cycle Time
tV Output Valid from Clock Low
tHO Output Hold Time
tDIS Output Disable Time
tHZ H¯¯O¯L¯D¯ to Output High Z
tCS ¯C¯S¯ High Time
tCSS ¯C¯S¯ Setup Time
tCSH ¯C¯S¯ Hold Time
50
50
125
125
DC
CL = 50pF
100
100
0
250
250
250
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Typ Max Units
ns
ns
ns
ns
3 MHz
50 ns
2 µs
2 µs
ns
ns
10 ms
250 ns
ns
250 ns
100 ns
ns
ns
ns
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2012 Rev. H
5 Page 
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A1 A0 0 0 0 1 R1 R0 0 0 ¯C¯S¯
DP7401
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A1 A0 1 0 0 0 R1 R0 0
High
0
¯C¯S¯
Voltage
Write
Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High
¯C¯S¯
0
1
0
1
0
0
A1
A0
1
1
1
0
R1
R0
P1
P0
¯C¯S¯
Voltage
Write
Cycle
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A1 A0 1 1 0 1 R1 R0 P1 P0 ¯C¯S¯
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A1 A0 0 0 1 0 0 0 P1 P0 I/D I/D
DATA
...
I/D I/D ¯C¯S¯
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after ¯C¯S¯ goes high.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2012 Rev. H
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet DP7401.PDF ] | |
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