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PDF DP7251 Data sheet ( Hoja de datos )

Número de pieza DP7251
Descripción Quad Digital Potentiometer
Fabricantes COPAL ELECTRONICS 
Logotipo COPAL ELECTRONICS Logotipo



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No Preview Available ! DP7251 Hoja de datos, Descripción, Manual

Quad Digital Potentiometer (DP) with
256 Taps and SPI Interface
DP7251
FEATURES
Four linear-taper digital potentiometers
254 resistor taps per potentiometer
End to end resistance 50kŸ or 100kŸ
Potentiometer control and memory access via
SPI interface
Low wiper resistance, typically 100Ÿ
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
SOIC 24-lead and TSSOP 24-lead
Industrial temperature range
For Ordering Information details, see page 14.
PIN CONFIGURATION
SOIC 24-Lead (W)
TSSOP 24-Lead (Y)
DESCRIPTION
The DP7251 is four Digital Potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a SPI serial
bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
register.
The DP7251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40°C to 85°C
industrial operating temperature range and offered in
a 24-lead SOIC and TSSOP package.
FUNCTIONAL DIAGRAM
SO 1
24 H¯¯O¯L¯D¯
A0 2
23 SCK
RW3 3
22 RL2
RH3 4
21 RH2
RL3 5
20 RW2
NC 6 DP 19 NC
VCC 7 7251 18 GND
RLO 8
17 RW1
RHO 9
16 RH1
RWO 10
15 RL1
¯C¯S¯ 11
14 A1
¯W¯P¯ 12
13 SI
CS
SCK
SI
SO
WP
A0
A1
HOLD
SPI BUS
INTERFACE
CONTROL
LOGIC
RH0 RH1 RH2 RH3
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
RW0
RW1
RW2
RW3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2017 Rev. F

1 page




DP7251 pdf
DP7251
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA = 25ºC, f = 1.0MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Parameter
Output Capacitance (SO)
Input Capacitance (¯C¯S¯, SCK, SI, ¯W¯P¯, H¯¯O¯L¯D¯, A0, A1)
Test Conditions Min Typ Max Units
VOUT = 0V
VIN = 0V
8 pF
6 pF
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
tSU
tH
tWH
tWL
fSCK
tLZ
tRI(1)
tFI(1)
tHD
tCD
tV
tHO
tDIS
tHZ
tCS
tCSS
tCSH
Parameter
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
H¯¯O¯L¯D¯ to Output Low Z
Input Rise Time
Input Fall Time
H¯¯O¯L¯D¯ Setup Time
H¯¯O¯L¯D¯ Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
H¯¯O¯L¯D¯ to Output High Z
¯C¯S¯ High Time
¯C¯S¯ Setup Time
¯C¯S¯ Hold Time
Test Conditions
CL = 50pF
Min Typ Max Units
50 ns
50 ns
125 ns
125 ns
DC 3 MHz
50 ns
2 µs
2 µs
100 ns
100 ns
200 ns
0 ns
250 ns
100 ns
250 ns
250 ns
250 ns
POWER UP TIMING (1)(2)
Over recommended operating conditions unless otherwise stated.
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
DP TIMING
Symbol Parameter
Min Max Units
tWRPO Wiper Response Time After Power Supply Stable 5 10 µs
tWRL Wiper Response Time After Instruction Issued
5 10 µs
Typ Max Units
1 ms
1 ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2017 Rev. F

5 Page





DP7251 arduino
Global Transfer Data Register (DR) to Wiper Control Register (WCR) (1)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 ¯C¯S¯
10
10
DP7251
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1
0
0
A
1
A
0
1 0 0 0RR
10
0
0
¯C¯S¯
High Voltage
Write Cycle
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0
0
A
1
A
0
1110RR
10
P
1
P
0
¯C¯S¯
High Voltage
Write Cycle
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A A 1 1 0 1 R R P P ¯C¯S¯
10
10 1 0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
¯C¯S¯ 0 1 0 1 0 0 A A 0 0 1 0 0 0 P P I/D I/D
10
10
DATA
...
I/D I/D ¯C¯S¯
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2017 Rev. F

11 Page







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