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PDF DP7241 Data sheet ( Hoja de datos )
| Número de pieza | DP7241 | |
| Descripción | Quad Digital Potentiometer | |
| Fabricantes | COPAL ELECTRONICS | |
| Logotipo |  |
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Quad Digital Potentiometer (DP) with
64 Taps and 2-wire Interface
DP7241
FEATURES
Four linear-taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5k, 10k, 50k or
100k
Potentiometer control and memory access via
2-wire interface (I2C like)
Low wiper resistance, typically 80W
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
20-lead SOIC and TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The DP7241 is four Digital Potentiometers
(DPs) integrated with control logic and 16 bytes
of NVRAM memory. Each DP consists of a series
of 63 resistive elements connected between
two externally accessible end points. The tap
points between each resistive element are connected
to the wiper outputs with CMOS switches. A separate
6-bit control register (WCR) independently controls
the wiper tap switches for each DP. Associated with
each wiper control register are four 6-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus (I2C-like). On power-up, the contents of the
first data register (DR0) for each of the four
potentiometers is automatically loaded into its
respective wiper control register (WCR).
The DP7241 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
SOIC 20 Lead (W)
TSSOP 20 Lead (Y)
RW0 1
20 VCC
RL0 2
19 RW3
RH0 3
18 RL3
A0 4
17 RH3
A2 5 CAT 16 A1
RW1 6 5241 15 A3
RL1 7
14 SCL
RH1 8
13 RW2
SDA 9
12 RL2
GND 10
11 RH2
SCL
SDA
A0
A1
A2
A3
FUNCTIONAL DIAGRAM
2-WIRE BUS
INTERFACE
CONTROL
LOGIC
RH0 RH1 RH2 RH3
WIPER
CONTROL
REGISTERS
NONVOLATILE
DATA
REGISTERS
RL0 RL1 RL2 RL3
RW0
RW1
RW2
RW3
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2011 Rev. P
1 page  
DP7241
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
tWR Write Cycle Time
Min Typ Max Units
5 ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the
device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Typ
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Max
Units
Cycles/Byte
Years
Volts
mA
Figure 1. Bus Timing
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
tSU:STO
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
Figure 3. Start/Stop Timing
SDA
SCL
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
START BIT
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
STOP BIT
5 Doc. No. MD-2011 Rev. P
5 Page 
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
SCL
SDA
RW Voltage Out
tWRID
DP7241
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 0 0 1 P1 P0 0 0 C 7 6 5 4 3 2 1 0 C T
A K K KO
RP
T
Write Wiper Control Register (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 0 1 0 P1 P0 0 0 C 7 6 5 4 3 2 1 0 C T
A K K KO
RP
T
Read Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 0 1 1 P1 P0 R1 R0 C 7 6 5 4 3 2 1 0 C T
AK
K KO
RP
T
Write Data Register (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
T 0 1 0 1 A3 A2 A1 A0 C 1 1 0 0 P1 P0 R1 R0 C 7 6 5 4 3 2 1 0 C T
AK
K KO
RP
T
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2011 Rev. P
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DP7241.PDF ] | |
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