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PDF CD82C85 Data sheet ( Hoja de datos )
| Número de pieza | CD82C85 | |
| Descripción | CMOS Static Clock Controller/Generator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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82C85
March 1997
CMOS Static Clock Controller/Generator
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors and Peripherals
• Complete Control Over System Operation for Very
Low System Power
- Stop-Oscillator
- Low Frequency
- Stop-Clock
- Full Speed Operation
• DC to 25MHz Operation (DC to 8MHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks
(Synchronized)
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• TTL Compatible Inputs/Outputs
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC
Package Options
• Single 5V Power Supply
• Operating Temperature Range
- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PART NUMBER
CS82C85
IS82C85
CD82C85
ID82C85
MD82C85/B
MR82C85/B
PACKAGE
28 Ld PLCC
24 Ld CERDIP
28 Pad CLCC
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
N28.45
N28.45
F24.3
F24.3
F24.3
J28.A
The Intersil 82C85 Static CMOS Clock Controller/Genera-
tor provides complete control of static CMOS system oper-
ating modes and supports full speed, slow, stop-clock and
stop-oscillator operation. While directly compatible with the
Intersil 80C86 and 80C88 16-bit Static CMOS Microproces-
sor Family, the 82C85 can also be used for general system
clock control.
For static system designs, separate signals are provided on
the 82C85 for stop (S0, S1, S2/STOP) and start (START)
control of the crystal oscillator and system clocks. A single
control line (SLO/FST) determines 82C85 fast (crystal/EFI
frequency divided by 3) or slow (crystal/EFI frequency
divided by 768) mode operation. Automatic maximum
mode 80C86 and 80C88 software HALT instruction decode
logic in the 82C85 enables software-based clock control.
Restart logic insures valid clock start-up and complete syn-
chronization of system clocks.
The 82C85 is manufactured using the Intersil advanced
Scaled SAJI IV CMOS process. In addition to clock control
circuitry, the 82C85 also contains a crystal controlled
oscillator (up to 25MHz), clock generation logic, complete
“Ready” synchronization and reset logic. This permits the
designer to tailor the system power-performance product to
provide optimum performance at low power levels.
Pinouts
24 LEAD CERDIP
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
CLK50 10
START 11
SLO/FST 12
24 VCC
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
28 LEAD PLCC, CLCC
TOP VIEW
4 3 2 1 28 27 26
RDY1 5
25 NC
READY 6
24 ASYNC
RDY2 7
23 EFI
AEN2 8
22 F/C
CLK 9
21 OSC
GND 10
20 RES
NC 11
19 RESET
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-297
File Number 2976.1
1 page  
82C85
until the oscillator signal amplitude reaches the X1 Schmitt
trigger input threshold voltage and 8192 cycles of the crystal
oscillator output are counted by an internal counter. After this
count is complete, the stopped outputs (CLK, CLK50, PCLK,
and OSC) start cleanly with the proper phase relationships.
Typically, any input signal which meets the START input tim-
ing requirements can be used to start the 82C85. In many
cases, this would be the INT output from an 82C59A CMOS
Priority Interrupt Controller (See Figure 1). This output,
which is active high, can be connected to both the 82C85
START pin and to the appropriate interrupt request input on
the microprocessor.
82C59A
INT
82C85
CLK
START S0
S1
S2/STOP
SLO/FST
VCC
80C86/88
INTR
CLK
PA0 PA1
82C55A
When the INT output becomes active, the oscillator/clock cir-
cuit on the 82C85 will restart. Upon completion of the appro-
priate restart sequence, the CLK signal to the CPU will
become active. The CPU can then respond to the still pend-
ing interrupt request.
If the 82C59A/82C85 restart combination is used in conjunc-
tion with an 82C55A STOP control, the 82C55A must be ini-
tialized prior to the 82C59A after reset. The 82C59A
interrupt output is driven high at reset, causing the 82C85 to
remain in the START mode regardless of the state of the
S2/STOP input. This will avoid stopping the 82C85 due to
negative transitions on the S2/STOP input which may occur
during a mode change on the 82C55A or during the opera-
tion of any peripheral I/O device prior to initialization.
Another method of insuring proper operation of the START
function upon reset or system initialization is to bias the
S2/STOP input low with an external pull-down resistor. The
S2/STOP input will remain low until driven high by the
82C55A port pin or by external logic. This insures that the
82C85 STOP command (HHH prior to LHH requirement on
the status inputs) will not be satisfied. To minimize power
dissipation in this case (using a pulldown resistor), the
S2/STOP input should be normally LOW and pulsed HIGH to
develop the necessary HHH-to-LHH STOP sequence. In this
manner, the output driving the S2/STOP input will be nor-
mally LOW and will not be driving to the opposite state of the
pull-down resistor.
FIGURE 1. CMOS PERIPHERAL CONTROL OF 82C85 STOP,
START AND SLOW/FAST OPERATIONS
Fast Mode
The most common operating mode for a system is the FAST
mode. In this mode, the 82C85 operates at the maximum fre-
quency determined by the main oscillator or EFI frequency.
TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT FOR STATIC CMOS OPERATING MODES
FAST
SLOW
STOP-CLOCK
STOP-OSC
CPU Frequency
5MHz
20 KHz
DC
DC
XTAL Frequency
15MHz
15MHz
15MHz
DC
ICC
82C85
24.7mA
16.9mA
14.1mA
24.4mA
80C88
23.8mA
173.0mA
106.6mA
106.6mA
82C82
1.7mA
6.5mA
1.0mA
1.0mA
82C86
1.4mA
14.0mA
1.0mA
1.0mA
82C88
3.5mA
14.3mA
3.8mA
3.8mA
82C52
151.2mA
72.0mA
1.0mA
1.0mA
82C54
943.0mA
915.0mA
3.5mA
1.0mA
82C55A
3.2mA
1.2mA
1.0mA
1.0mA
82C59A
580.0mA
520.0mA
1.0mA
1.0mA
74HCXX + other
2.9mA
10.0mA
90.0mA
90.0mA
HM-6516
820.0mA
32.0mA
1.9mA
1.9mA
HM-6616
6.3mA
52.5mA
12.0mA
12.0mA
Total
66.8mA
18.9mA
14.3mA
244.7mA
All measurements taken at room temperature, VCC = +5.0V. Power supply current levels will be dependent upon system configuration and
frequency of operation.
4-301
5 Page 
82C85
AC Electrical Specifications
VCC = 5V ±10%;TA = 0oC to +70oC (C82C85);
TA = -40oC to +85oC (I82C85);
TA = -55oC to +125oC (M82C85)
LIMITS
SYMBOL
PARAMETER
MIN MAX
TIMING REQUIREMENTS
(1) TEHEL
External Frequency HIGH Time
15 -
(2) TELEH
External Frequency LOW Time
15 -
(3) TELEL
(4) TEFIDC
(5) Fx
(6) TR1VCL
(7) TR1VCH
(8) TR1VCL
(9) TCLR1X
(10) TAYVCL
(11) TCLAYX
(12) TA1VR1V
(13) TCLA1X
(14) TYHEH
(15) TEHYL
(16) TYHYL
(17) TI1HCL
(18) TSVCH
(19) TCHSV
(20) TRSVCH
(21) TSHSL
(22) TSFPC
(23) TSTART
(24) TSTOP
EFI or Crystal Period
External Frequency Input Duty Cycle
Crystal Frequency
RDY1, RDY2 Active Setup to CLK
RDY1, RDY2 Active Setup to CLK
RDY1, RDY2 Inactive Setup to CLK
RDY1, RDY2 Hold to CLK
ASYNC Setup to CLK
ASYNC Hold to CLK
AEN1, AEN2 Setup to RDY1, RDY2
AEN1, AEN2 Hold to CLK
CSYNC Setup to EFI
CSYNC Hold to EFI
CSYNC Pulse Width
RES Setup to CLK
S0, S1, S2/STOP Setup to CLK
S0, S1, S2/STOP Hold to CLK
RES, START Setup to CLK
RES (Low) or START (High) Pulse Width
SLO/FST Setup to PCLK
RES or START Valid to CLK Low
STOP Command Valid to CLK High
TIMING RESPONSES
(25) TCLCL
CLK/CLK50 Cycle Period
(26) TCHCL
CLK HIGH Time
40
45
2.4
35
35
35
0
50
0
15
0
10
10
2TELEL
65
35
35
65
TCLCLs3
TEHEL + 100
2TELEL + 2
2TCHCH +
TRSVCH
125
(1/3 TCLCL)+2
-
55
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3TCHCH
+ 34
-
-
UNITS
CONDITIONS
ns
ns
ns
%
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
90%-90% VIN, Note 1,
f = 25MHz
10%-10% VIN, Note 1,
f = 25MHz
Note 1
f = 25MHz, Note 1
Note 1
ASYNC = HIGH
ASYNC = LOW
Note 2
Note 2
Note 2
TCHCH = TCLCL
ns Note 1
ns
4-307
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CD82C85.PDF ] | |
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