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PDF SC7313S Data sheet ( Hoja de datos )
| Número de pieza | SC7313S | |
| Descripción | 4-CH OUTPUT STEREO AUDIO PROCESSOR | |
| Fabricantes | Silan Microelectronics | |
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Hay una vista previa y un enlace de descarga de SC7313S (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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SC7313
4-CH OUTPUT STEREO AUDIO PROCESSOR WITH 3 STEREO INPUTS AND
TONE/VOLUME CONTROL
DESCRIPTION
The SC7313 is a volume, tone (bass and treble), balance (left/right) and
fader (front/rear) processor for quality audio applications in car radio and
Hi-Fi systems. Selectable input gain and external loudness function are
provided. Control is accomplished by serial I2C bus microprocessor
interface. The AC signal settings is obtained by resistor networks and
switches combined with operational amplifiers. Due to the used CMOS
technology, low distortion, low noise and low DC stepping are obtained.
FEATURES
* Input multiplexer:
--3 stereo inputs
--Selectable input gain
* Four speaker attenuators:
--4 independent speakers control in 1.25dB steps for balance and
fader facilities
--Independent mute function
* All functions programmable via serial I2C Bus
* Loudness function
* Volume control in 1.25dB steps
* Treble and bass control
* Input and output for external equalizer or noise reduction system
ORDERING INFORMATION
Device
SC7313
SC7313S
Package
DIP-28-600-2.54
SOP-28-375-1.27
BLOCK DIAGRAM
7 17
L1
15
L2
14
L3
13
R3
9
R2
10
R1
11
Input
Selection
&
Gain
Control
CREF
1 Reference
16 12 19 18 4 25 23
Volume &
Loudness
Bass
Treble
Speaker/
ATT
Serial Bus Decoder + Latches
SCL 28
SDA
27
DGND 26
Volume &
Loudness
Bass
Treble
Spaker/
ATT
2
3
68
21 20
5
22 24
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.2 2007.03.09
Page 1 of 14
1 page  
SC7313
APPLICATION NOTES
1. I2C BUS INTERFACE
The data transmitted from the microprocessor to SC7313 is through the 2 wires I2C bus interface. The 2 wires
I2C BUS is composed of two lines SDA and SCL (the positive supply voltage should be connected to a pull-up
resistor).
2. DATA VALIDITY
The data of the SDA line must be stable during the high period of the clock, as shown in Figure 17. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Fig. 17 Data Validity on the I2C BUS
3. START AND STOP CONDITIONS
As shown in Figure 18, a start condition is a falling edge of the SDA line while SCL is HIGH. The stop
condition is a rising edge of the SDA line while SCL is HIGH.
Fig. 18 Timing diagram of I2C BUS
4. BYTE FORMAT
Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge
bit. The MSB is transferred first.
5. ACKNOWLEDGE
During the acknowledge, the master(microprocessor) puts a resistive HIGH level on the SDA line. The
peripheral(audioprocessor) that acknowledges has to pull-down(LOW) the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during this clock pulse.
The audioprocessor which has been addressed has to generate an acknowledge after received each byte ,
otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.2 2007.03.09
Page 5 of 14
5 Page 
TEST AND TYPICAL APPLICATION CIRCUIT
SC7313
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.2 2007.03.09
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SC7313S.PDF ] | |
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