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PDF KAC-12040 Data sheet ( Hoja de datos )

Número de pieza KAC-12040
Descripción CMOS Image Sensor
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KAC-12040
4000 (H) x 3000 (V)
CMOS Image Sensor
Description
The KAC−12040 Image Sensor is a high-speed 12 megapixel
CMOS image sensor in a 4/3optical format based on a 4.7 mm 5T
CMOS platform. The image sensor features very fast frame rate,
excellent NIR sensitivity, and flexible readout modes with multiple
regions of interest (ROI). The readout architecture enables use of 8, 4,
or 2 LVDS output banks for full resolution readout of 70 frames per
second.
Each LVDS output bank consists of up to 8 differential pairs
operating at 160 MHz DDR for a 320 Mbps data rate per pair.
The pixel architecture allows rolling shutter operation for motion
capture with optimized dynamic range or global shutter for precise
still image capture.
Table 1. GENERAL SPECIFICATIONS
Parameter
Typical Value
Architecture
5T Global Shutter CMOS
Resolution
12 Megapixels
Aspect Ratio
4:3
Pixel Size
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Active Image Size
4.7 mm (H) × 4.7 mm (V)
4224 (H) × 3192 (V)
4016 (H) × 3016 (V)
4000 (H) × 3000 (V)
18.8 mm (H) × 14.1 mm (V)
23.5 mm (Diagonal), 4/3Optical Format
Master Clock Input Speed
5 MHz to 50 MHZ
Maximum Pixel Clock Speed
Number of LVDS Outputs
160 MHz DDR LVDS, 320 Mbps
64 Differential Pairs
Number of Output Banks
8, 4, or 2
Frame Rate, 12 Mp
1−70 fps 10 bits
1−75 fps 8 bits
Charge Capacity
16,000 electrons
Quantum Efficiency
KAC−12040−CBA
KAC−12040−ABA
Read Noise
(at Maximum LVDS Clock)
40%, 47%, 45% (470, 540, 620 nm)
53%, 15%, 10% (500, 850, 900 nm)
3.7 erms, Rolling Shutter
25.5 erms, Global Shutter
Dynamic Range
73 dB, Rolling Shutter
56 dB, Global Shutter
Blooming Suppression
> 10,000x
Image Lag
1.3 electron
Digital Core Supply
2.0 V
Analog Core Supply
1.8 V
Pixel Supply
2.8 V & 3.5 V
Power Consumption
1.5 W for 12 Mp @ 70 fps 10 bits
Package
267 Pin Ceramic Micro-PGA
Cover Glass
AR Coated, 2-sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 5
1
www.onsemi.com
Figure 1. KAC−12040 CMOS Image Sensor
Features
Global Shutter and Rolling Shutter
Very Fast Frame Rate
High NIR Sensitivity
Multiple Regions of Interest
Interspersed Video Streams
Applications
Machine Vision
Intelligent Transportation Systems
Surveillance
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Publication Order Number:
KAC−12040/D

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KAC-12040 pdf
KAC−12040
Table 4. PRIMARY PIN DESCRIPTION
Pin
Name
Type
Description
AB09
RESETN
DI Sensor Reset (0 V = Reset State)
E07 CLK_In1
DI Sensor Input Clk_In1 (45−50 MHz)
D08 CLK_In2
DI Sensor Input Clk_In2 (Connect to Clk1)
AB08
TRIGGER
DI Trigger Input (Optional)
AA05
SCLK
DI SPI Master Clock
AA08
MOSI
DI SPI Master Output, Slave Input
AA07
MISO
DO SPI Master Input, Slave Output
AA06
CSN
DI SPI Chip Select (0 V = Selected)
AA14
AA15
ADC_Ref1
ADC_Ref2
AO 4.02 kW ±1% Resistor between Ref1 & Ref2
AO 4.02 kW ±1% Resistor between Ref1 & Ref2
AB07
MSO
DO Mechanical Shutter Output Sync (Optional)
AB06
FLO
DO Flash Output Sync (Optional)
E05 FEN DO Frame Enable Reference Output (Optional)
E06 LEN DO Line Enable Reference Output (Optional)
1. DI = Digital Input, DO = Digital Output, AO = Analog Output.
2. Tie unused DI pins to Ground, NC unused DO pins.
3. By default Clk_In2 should equal Clk_In1 and should be the same source clock.
4. The RESETN pin has a 62 kW internal pull-up resistor, so if left floating the chip will not be in reset mode.
5. The TRIGGER pin has an internal 100 kW pull down resistor. If left floating (and at default polarity) then the sensor state will not be affected
by this pin (i.e. defaults to ‘not triggered’ mode if floated).
6. All of the DI and DO pins nominally operate at 0 V 2.0 V and are associated with the VDD_DIG power supply.
Table 5. POWER PIN DESCRIPTION
Name
Voltage
Pins
VDD_LVDS
3.3 V D
C04, C05, C23, C24, D04, D24, E04, E24, AA04, AA24,
AB04, AB24, AC04, AC05 AC23, AC24
VDD_DIG
2.0 V D
C18, C19, D18, D19, E18, AA18, AB18, AB19, AC18, AC19,
C20, C21, C22, D20, D21, D22, D23, E20, E21, E22, AA20,
AA21, AA22, AB20, AB21, AB22, AB23, AC20, AC21,
AC22, AB15, E08
AVDD_HV
3.5 V A
C11, D11, E11, AA11, AB11, AC11, C10, D10, E10, AA10,
AB10, AC10
Vref_P
2.8 V A
C13, D13, E13, AA13, AB13, AC13
AVDD_LV
1.8 V A
C17, D16, D17, E17, AA17, AB16, AB17, AC17
Vpixel_low
0 V E09
VSS
No Connect
0 V C12, C14, D12, D14, E12, AA12, AB12, AB14, AC12, AC14,
E15, D15, AA09, A02, A14, A26, B14, C03, C06, C25, D03,
D25, E03, E19, E23, E25, AA03, AA19, AA23, AA25, AB25,
AC03, AC06, AC25, AD14, AE02, AE14, AE26
NA A01, AC09, E14, E16, C09, D09, D05, D06, D07, AA16,
AB05
Description
LVDS Output Supply
Digital Core Supply
Pixel Supply 1
Pixel Supply 2
Analog Low Voltage Supply
Pixel Supply 3. Combine with VSS for
normal operation. Can be pulsed for
Extended Dynamic Range Operation.
Sensor Ground Reference
Unused and test-only pins. These
pins must be floated.
www.onsemi.com
5

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KAC-12040 arduino
Dark Current vs. Temperature
KAC−12040
NOTE: “Dbl” denotes an approximate doubling temperature for the dark current for the displayed temperature range.
Figure 8. Dark Current vs. Temperature
Power vs. Frame Rate
The most effective method to use the maximum PLL2
speed (313 320 MHz) and control frame rate with
minimum Power and maximum image quality is to adjust
Vertical Blanking. (register 01F1h). Unnecessary chip
operations are suspended during Vertical Blanking
conserving significant power consumption and also
minimizing the image storage time on the storage node when
in Global Shutter Operation.
NOTE: The LVDS clock is ½ the PLL2 clock speed.
Figure 9. Power vs. Frame Rate, 10 bit Mode
www.onsemi.com
11

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