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PDF AP0100CS Data sheet ( Hoja de datos )
| Número de pieza | AP0100CS | |
| Descripción | High-Dynamic Range (HDR) Image Signal Processor | |
| Fabricantes | ON Semiconductor | |
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AP0100CS HDR: Image Signal Processor (ISP)
Features
AP0100CS High-Dynamic Range (HDR) Image
Signal Processor (ISP)
AP0100CS Datasheet, Rev. 6
For the latest product datasheet, please visit www.onsemi.com
Features
• Up to 1.2Mp (1280x960) ON Semiconductor sensor
support
• 45 fps at 1.2Mp, 60 fps at 720p
• Optimized for operation with HDR sensors.
• Color and gamma correction
• Auto exposure, auto white balance, 50/60 Hz auto
flicker detection and avoidance
• Adaptive Local Tone Mapping (ALTM)
• Programmable Spatial Transform Engine (STE).
• Pre-rendered Graphical Overlay
• Two-wire serial programming interface (CCIS)
• Interface to low-cost Flash or EEPROM through SPI
bus (to configure and load patches, etc.)
• High-level host command interface
• Standalone operation supported
• Up to 5 GPIO
• Fail-safe IO
• Multi-Camera synchronization support
• Integrated video encoder for NTSC/PAL with overlay
capability and 10-bit I-DAC
Applications
• IP cam and CCTV - HD
• Enables CCTV -HD w/ MP sensor
Table 1:
Key Performance Parameters
Parameter
Value
Primary camera
interfaces
Parallel and HiSPi
Primary camera input
RAW12 Linear/RAW12, RAW14 (HiSPi
format only) Companded
Output interface
Output format
Analog composite, up to 16-bit
parallel digital output
YUV422 8-bit,10-bit, and 10-, 12-bit
tone-mapped Bayer
Maximum resolution 1280x960 (1.2 Mp)
NTSC output
720H x 487V
PAL output
720H x 576V
Input clock range
Supply voltage
6-30 MHz
VDDIO_S
VDDIO_H
VDD_REG
VDD
VDD_PLL
VDD_DAC
VDDIO_OTPM
1.8 or 2.8 V nominal
2.5 or 3.3 V nominal
1.8 V nominal
1.2 V nominal
1.2 V nominal
1.2V nominal
2.5 or 3.3 V nominal
VDDA_DAC
3.3 V nominal
Operating temp.
Power consumption
VDD_PHY
2.8 V nominal
–30°C to +70°C
185 mW
Notes: 1.
AP0100CS/D Rev. 6, 1/16 EN
1 ©Semiconductor Components Industries, LLC 2016,
1 page  
AP0100CS HDR: Image Signal Processor (ISP)
System Interfaces
Figure 2:
Typical Parallel Configuration
1.8V
Sensor IO ( R egulator
power
IP)
1 . 2 V ( R egulator OP)
P ower up C ore, P LL.
and DAC digital
DAC
analog
power
OTPM
power
Host IO
power
VDDIO _S
M_S CLK
M_S DATA
EXTCLK_OUT
RESET_BAR_OUT
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
TRIGGER_OUT
G ND_REG
GND
VDDIO _H
S CLK
S DATA
S ADDR
EXTCLK
XTAL
S P I_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
FRAME_SYNC
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRST_BAR5
VDDIO_S6 VDD_REG4 LDO_OP4
VDDIO_OTPM VDDIO_H
VDDIO_DAC
Notes:
1. This typical configuration shows only one scenario out of multiple possible variations for this
device.
2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;
however, greater values may be used for slower transmission speed.
3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.
4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The
capacitors should be ceramic and need to have X5R or X7R dielectric.
5. TRST_BAR connects to GND for normal operation.
6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply
are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay-
out and design consideration
AP0100CS/D Rev. 6, Pub. 1/16 EN
5 ©Semiconductor Components Industries, LLC,2016.
5 Page 
AP0100CS HDR: Image Signal Processor (ISP)
On-Chip Regulator
On-Chip Regulator
The AP0100CS has an on-chip regulator, the output from the regulator is 1.2 V and
should only be used to power up the AP0100CS. It is possible to bypass the regulator and
provide power to the relevant pins that need 1.2 V. Figure 5 shows how to configure the
AP0100CS to bypass the internal regulator.
Figure 5: External Regulator
Sensor IO
power
Host IO
power
Extern1a.l2sVuppliHepdooswteIOr panDoawAlCoergpPoHwYeOproTwPMer
Host IO
power
VDDIO _S
M_S CLK
M_S DATA
EXTCLK_OUT
RESET_BAR_OUT
FV _IN
LV_IN
PIXCLK _IN
DIN [11:0]
TRIGGER_OUT
CLK_N CLK_P
DATA0_N DATA0_P
DATA1_N DATA1_P
GND
VDDIO _H
S CLK
S DATA
S ADDR
S TANDBY
EXTCLK
XTAL
S P I_CS_BAR
SPI_CLK
SPI_SDO
SPI_SDI
FV_OUT
LV_OUT
PIXCLK_OUT
D OUT[15:0]
DAC_POS
DAC_NEG
DAC_REF
FRAME_SYNC
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
TRST_BAR
Table 5:
The following table summarizes the key signals when using/bypassing the regulator.
Key Signals When Using the Regulator
Signal Name
VDD_REG
ENLDO
FB_SENSE
LDO_OP
EXT_REG
Internal Regulator
1.8 V
Connect to 1.8 V (VDD_REG)
1.2 V (output)
1.2 V (output)
GND
External Regulator
Connect to VDDIO_H
GND
Float
Float
Connect to VDDIO_H
AP0100CS/D Rev. 6, Pub. 1/16 EN
11
©Semiconductor Components Industries, LLC,2016.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AP0100CS.PDF ] | |
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