DataSheet.es    


PDF AD7891 Data sheet ( Hoja de datos )

Número de pieza AD7891
Descripción 12-Bit High Speed Data Acquisition System
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



Hay una vista previa y un enlace de descarga de AD7891 (archivo pdf) en la parte inferior de esta página.


Total 21 Páginas

No Preview Available ! AD7891 Hoja de datos, Descripción, Manual

a
LC2MOS 8-Channel, 12-Bit
High Speed Data Acquisition System
FEATURES
Fast 12-Bit ADC with 1.6 s Conversion Time
8 Single-Ended Analog Input Channels
Overvoltage Protection on Each Channel
Selection of Input Ranges:
؎5 V, ؎10 V for AD7891-1
0 to +2.5 V, 0 to +5 V, ؎2.5 V for AD7891-2
Parallel and Serial Interface
On-Chip Track/Hold Amplifier
On-Chip Reference
Single-Supply, Low Power Operation (100 mW Max)
Power-Down Mode (75 W Typ)
APPLICATIONS
Data Acquisition Systems
Motor Control
Mobile Communication Base Stations
Instrumentation
VIN1A
VIN1B
VIN2A
VIN2B
VIN3A
VIN3B
VIN4A
VIN4B
VIN5A
VIN5B
VIN6A
VIN6B
VIN7A
VIN7B
VIN8A
VIN8B
AD7891
FUNCTIONAL BLOCK DIAGRAM
VDD VDD
REF OUT/
REF IN
REF GND
AD7891
2.5V
REFERENCE
STANDBY
M
U
X
TRACK/HOLD
ADDRESS
DECODE
CONTROL LOGIC
12-BIT
ADC
CLOCK
DATA /
CONTROL
LINES
WR CS RD EOC CONVST MODE AGND AGND DGND
GENERAL DESCRIPTION
The AD7891 is an 8-channel, 12-bit data acquisition system
with a choice of either parallel or serial interface structure. The
part contains an input multiplexer, an on-chip track/hold ampli-
fier, a high speed 12-bit ADC, a 2.5 V reference, and a high
speed interface. The part operates from a single 5 V supply and
accepts a variety of analog input ranges across two models, the
AD7891-1 (± 5 V and ± 10 V) and the AD7891-2 (0 V to +2.5 V,
0 V to +5 V, and ± 2.5 V).
The AD7891 provides the option of either a parallel or serial
interface structure determined by the MODE pin. The part
has standard control inputs and fast data access times for both
the serial and parallel interfaces, ensuring easy interfacing to
modern microprocessors, microcontrollers, and digital signal
processors.
In addition to the traditional dc accuracy specifications, such as
linearity, full-scale and offset errors, the part is also specified for
dynamic performance parameters, including harmonic distortion
and signal-to-noise ratio.
Power dissipation in normal mode is 82 mW typical; in
the standby mode, this is reduced to 75 mW typ. The part is
available in a 44-terminal MQFP and a 44-lead PLCC.
PRODUCT HIGHLIGHTS
1. The AD7891 is a complete monolithic 12-bit data acquisition
system that combines an 8-channel multiplexer, 12-bit ADC,
2.5 V reference, and track/hold amplifier on a single chip.
2. The AD7891-2 features a conversion time of 1.6 ms and an
acquisition time of 0.4 ms. This allows a sample rate of
500 kSPS when sampling one channel and 62.5 kSPS when
channel hopping. These sample rates can be achieved using
either a software or hardware convert start. The AD7891-1
has an acquisition time of 0.6 ms when using a hardware
convert start and an acquisition time of 0.7 ms when using a
software convert start. These acquisition times allow sample
rates of 454.5 kSPS and 435 kSPS, respectively, for hardware
and software convert start.
3. Each channel on the AD7891 has overvoltage protection. This
means an overvoltage on an unselected channel does not affect
the conversion on a selected channel. The AD7891-1 can
withstand overvoltages of ± 17 V.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.

1 page




AD7891 pdf
AD7891
TIMING CHARACTERISTICS1, 2
Parameter
A, B, Y Versions
Unit
Test Conditions/Comments
tCONV
Parallel Interface
t1
t2
t3
t4
t5
t6
t7
t8
t93
t104
1.6
0
35
25
5
0
35
55
35
25
5
30
ms max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Conversion Time
CS to RD/WR Setup Time
Write Pulse Width
Data Valid to Write Setup Time
Data Valid to Write Hold Time
CS to RD/WR Hold Time
CONVST Pulse Width
EOC Pulse Width
Read Pulse Width
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
Serial Interface
t11
t123
t13
t14
t153
t163
t17
t184
t18A4
t19
t20
t21
t22
30
20
25
25
5
15
20
0
30
0
30
20
15
10
30
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
RFS Low to SCLK Falling Edge Setup Time
RFS Low to Data Valid Delay
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Rising Edge to Data Valid Hold Time
SCLK Rising Edge to Data Valid Delay
RFS to SCLK Falling Edge Hold Time
Bus Relinquish Time after Rising Edge of RFS
Bus Relinquish Time after Rising Edge of SCLK
TFS Low to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Setup Time
Data Valid to SCLK Falling Edge Hold Time
TFS Low to SCLK Falling Edge Hold Time
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1 ns (10% to
90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 2, 3, and 4.
3Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
TO
OUTPUT
PIN
50pF
1.6V
200A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4– REV. D

5 Page





AD7891 arduino
AD7891
CONVERTER DETAILS
The AD7891 is an 8-channel, high speed, 12-bit data acquisi-
tion system. It provides the user with signal scaling, multiplexer,
track/hold, reference, ADC, and high speed parallel and serial
interface logic functions on a single chip. The signal condition-
ing on the AD7891-1 allows the part to accept analog input
ranges of ± 5 V or ± 10 V when operating from a single supply.
The input circuitry on the AD7891-2 allows the part to handle
input signal ranges of 0 V to +2.5 V, 0 V to +5 V, and ±2.5 V
again while operating from a single 5 V supply. The part requires
a 2.5 V reference that can be provided from the parts own internal
reference or from an external reference source.
Conversion is initiated on the AD7891 either by pulsing the
CONVST input or by writing a Logic 1 to the SWCONV bit of
the control register. When using the hardware CONVST input,
the on-chip track/hold goes from track to hold mode and the
conversion sequence is started on the rising edge of the CONVST
signal. When a software conversion start is initiated, an internal
pulse is generated, delaying the track/hold acquisition point and
the conversion start sequence until the pulse is timed out. This
internal pulse is initiated (goes from low to high) whenever a
write to the AD7891 control register takes place with a 1 in the
SWCONV bit. It then starts to discharge and the track/hold
cannot go into hold and conversion cannot be initiated until the
pulse signal goes low. The internal pulse duration is equal to the
track/hold acquisition time. This allows the user to obtain a
valid result after changing channels and initiating a conversion
in the same write operation.
The conversion clock for the part is internally generated and
conversion time for the AD7891 is 1.6 ms from the rising edge of
the hardware CONVST signal. The track/hold acquisition time
for the AD7891-1 is 600 ns, while the track/hold acquisition
time for the AD7891-2 is 400 ns. To obtain optimum perfor-
mance from the part, the data read operation should not occur
during the conversion or during the 100 ns prior to the next
conversion. This allows the AD7891-1 to operate at throughput
rates up to 454.5 kSPS and the AD7891-2 to operate at through-
put rates up to 500 kSPS in the parallel mode and achieve data
sheet specifications. In the serial mode, the maximum achievable
throughput rate for both the AD7891-1 and the AD7891-2 is
357 kSPS (assuming a 20 MHz serial clock).
All unused analog inputs should be tied to a voltage within the
nominal analog input range to avoid noise pickup. For mini-
mum power consumption, the unused analog inputs should be
tied to AGND.
INTERFACE INFORMATION
The AD7891 provides two interface options, a 12-bit parallel
interface and a high speed serial interface. The required inter-
face mode is selected via the MODE pin. The two interface
modes are discussed in the following sections.
Parallel Interface Mode
The parallel interface mode is selected by tying the MODE
input to a logic high. Figure 2 shows a timing diagram illustrating
the operational sequence of the AD7891 in parallel mode for a
hardware conversion start. The multiplexer address is written to
the AD7891 on the rising edge of the WR input. The on-chip
track/hold goes into hold mode on the rising edge of CONVST;
conversion is also initiated at this point. When the conversion is
complete, the end of conversion line (EOC) pulses low to indi-
cate that new data is available in the AD7891s output register.
This EOC line can be used to drive an edge-triggered interrupt
of a microprocessor. CS and RD going low accesses the 12-bit
conversion result. In systems where the part is interfaced to a
gate array or ASIC, this EOC pulse can be applied to the CS
and RD inputs to latch data out of the AD7891 and into the
gate array or ASIC. This means the gate array or ASIC does not
need any conversion status recognition logic, and it also elimi-
nates the logic required in the gate array or ASIC to generate
the read signal for the AD7891.
CONVST (I)
t6 t7
EOC (O)
t CONV
CS (O)
t1 t5
t2
WR (I)
t1 t5
t8
RD (I)
t3
DB0 TO DB11
(I/O)
VALID DATA
INPUT
NOTE
I = INPUT
O = OUTPUT
t4
t9
VALID DATA
OUTPUT
Figure 2. Parallel Mode Timing Diagram
t 10
–10–
REV. D

11 Page







PáginasTotal 21 Páginas
PDF Descargar[ Datasheet AD7891.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
AD789012-Bit Serial Data Acquisition SystemAnalog Devices
Analog Devices
AD789112-Bit High Speed Data Acquisition SystemAnalog Devices
Analog Devices
AD7892LC2MOS Single Supply/ 12-Bit 600 kSPS ADCAnalog Devices
Analog Devices
AD7893LC2MOS 12-Bit/ Serial 6 us ADC in 8-Pin PackageAnalog Devices
Analog Devices

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar