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PDF MAX1282 Data sheet ( Hoja de datos )
| Número de pieza | MAX1282 | |
| Descripción | Serial 12-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
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19-1688; Rev 0; 5/00
EVAALVUAAILTAIOBNLEKIT
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
General Description
The MAX1282/MAX1283 12-bit analog-to-digital convert-
ers (ADCs) combine a 4-channel analog-input multiplexer,
high-bandwidth track/hold (T/H), and serial interface with
high conversion speed and low power consumption. The
MAX1282 operates from a single +4.5V to +5.5V supply;
the MAX1283 operates from a single +2.7V to +3.6V sup-
ply. Both devices’ analog inputs are software configurable
for unipolar/bipolar and single-ended/pseudo-differential
operation.
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1282/
MAX1283 use an external serial-interface clock to perform
successive-approximation analog-to-digital conversions.
The devices feature an internal +2.5V reference and a ref-
erence-buffer amplifier with a ±1.5% voltage-adjustment
range. An external reference with a 1V to VDD range may
also be used.
The MAX1282/MAX1283 provide a hardwired SHDN pin
and four software-selectable power modes (normal opera-
tion, reduced power (REDP), fast power-down (FASTPD),
and full power-down (FULLPD)). These devices can be
programmed to automatically shut down at the end of a
conversion or to operate with reduced power. When using
the power-down modes, accessing the serial interface
automatically powers up the devices, and the quick turn-
on time allows them to be shut down between all conver-
sions.
The MAX1282/MAX1283 are available in 16-pin TSSOP
packages.
Features
♦ 4-Channel Single-Ended or 2-Channel
Pseudo-Differential Inputs
♦ Internal Multiplexer and Track/Hold
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1282)
+2.7V to +3.6V (MAX1283)
♦ Internal +2.5V Reference
♦ 400kHz Sampling Rate (MAX1282)
♦ Low Power: 2.5mA (400ksps)
1.3mA (REDP)
0.9mA (FASTPD)
2µA (FULLPD)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 16-Pin TSSOP Package
Ordering Information
PART
TEMP.
RANGE
MAX1282BCUE
MAX1282BEUE
MAX1283BCUE
MAX1283BEUE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-
PACKAGE
16 TSSOP
16 TSSOP
16 TSSOP
16 TSSOP
INL
(LSB)
±1
±1
±1
±1
Applications
Portable Data Logging
Data Acquisition
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
Process Control
Typical Operating Circuit appears at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configuration
TOP VIEW
VDD1 1
CH0 2
CH1 3
CH2 4
CH3 5
COM 6
SHDN 7
REF 8
MAX1282/
MAX1283
16 VDD2
15 SCLK
14 CS
13 DIN
12 SSTRB
11 DOUT
10 GND
9 REFADJ
TSSOP
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
1 page  
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1283 (continued)
(VDD1 = VDD2 = +2.7V to +3.6V, COM = GND, fOSC = 4.8MHz, 50% duty cycle, 16 clocks/conversion cycle (300ksps), external
+2.5V at REF, REFADJ = VDD1, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
SYMBOL
CONDITIONS
tCONV
tACQ
Normal operating mode
Normal operating mode
Serial Clock Frequency
fSCLK
Duty Cycle
ANALOG INPUTS (CH3–CH0, COM)
Normal operating mode
Input Voltage Range, Single
Ended and Differential (Note 6)
VCH_
Unipolar, VCOM = 0
Bipolar, VCOM or VCH_ = VREF/2,
referenced to COM or CH_
Multiplexer Leakage Current
Input Capacitance
INTERNAL REFERENCE
On/off leakage current, VCH_ = 0 or VDD1
REF Output Voltage
REF Short-Circuit Current
VREF TA = +25°C
REF Output Temperature
Coefficient
TC VREF
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
0 to 0.75mA output load
REFADJ Input Range
For small adjustments, from 1.22V
REFADJ Buffer Disable
Threshold
To power down the internal reference
Buffer Voltage Gain
EBXufTfeErRVNoAltaLgReEGFaEinRENCE (reference buffer disabled, reference applied to REF)
REF Input Voltage Range
(Note 8)
REF Input Current
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
VINH
Input Low Voltage
VINL
Input Hysteresis
VHYST
Input Leakage
IIN
Input Capacitance
CIN
VREF = 2.500V, fSCLK = fMAX
VREF = 2.500V, fSCLK = 0
In full power-down mode, fSCLK = 0
VIN = 0 or VDD2
MIN TYP MAX UNITS
3.3 µs
625 ns
10 ns
<50 ps
0.5 4.8 MHz
40 60 %
VREF
±VREF/2
±0.001 ±1
18
V
µA
pF
2.480 2.500 2.520
15
V
mA
±15 ppm/°C
0.1 2.0
4.7 10
0.01 10
1.22
±100
mV/mA
µF
µF
V
mV
1.4 VDD1 - 1.0 V
2.05 V/V
2.05 V/V
1.0
VDD1 +
50mV
V
200 350
320
5
µA
2.0
0.8
0.2
±1
15
V
V
V
µA
pF
_______________________________________________________________________________________ 5
5 Page 
300ksps/400ksps, Single-Supply, 4-Channel,
Serial 12-Bit ADCs with Internal Reference
Detailed Description
The MAX1282/MAX1283 ADCs use a successive-
approximation conversion technique and input T/H cir-
cuitry to convert an analog signal to a 12-bit digital out-
put. A flexible serial interface provides easy interface to
microprocessors (µPs). Figure 3 shows a functional dia-
gram of the MAX1282/MAX1283.
Pseudo-Differential Input
The equivalent circuit of Figure 4 shows the MAX1282/
MAX1283’s input architecture, which is composed of a
T/H, input multiplexer, input comparator, switched-
capacitor DAC, and reference.
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1 and
CH2/CH3. Configure the channels according to Tables
1 and 2.
The MAX1282/MAX1283 input configuration is pseudo-
differential because only the signal at IN+ is sampled.
The return side (IN-) is connected to the sampling
capacitor while converting and must remain stable
within ±0.5LSB (±0.1LSB for best results) with respect
to GND during a conversion.
If a varying signal is applied to the selected IN-, its
amplitude and frequency must be limited to maintain
accuracy. The following equations express the relation-
ship between the maximum signal amplitude and its
frequency to maintain ±0.5LSB accuracy. Assuming a
sinusoidal signal at IN-, the input voltage is determined
by:
νIN− = (VIN −)sin(2πft)
The maximum voltage variation is determined by:
( )max
d νIN −
dt
= VIN
−
2πf ≤
1LSB
tCONV
=
VREF
212 tCONV
A 0.65Vp-p, 60Hz signal at IN- will generate a ±0.5LSB
error when using a +2.5V reference voltage and a
2.5µs conversion time (15 / fSCLK). When a DC refer-
ence voltage is used at IN-, connect a 0.1µF capacitor
to GND to minimize noise at the input.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit has been entered. At the end of the acquisition
interval, the T/H switch opens, retaining charge on
CHOLD as a sample of the signal at IN+. The conver-
sion interval begins with the input multiplexer switching
CHOLD from IN+ to IN-. This unbalances node ZERO at
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to VDD1 / 2 within the limits of 12-bit resolu-
tion. This action is equivalent to transferring a
12pF ✕ (VIN+ - VIN-) charge from CHOLD to the binary-
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
CS 14
SCLK 15
DIN 13
SHDN 7
CH0 2
CH1 3
CH2 4
CH3 5
COM 6
REFADJ 9
REF 8
INPUT
SHIFT
REGISTER
CONTROL
LOGIC
INT
CLOCK
ANALOG
INPUT
MUX
OUTPUT
SHIFT
REGISTER
T/H
CLOCK
IN
12-BIT
SAR ADC
OUT
REF
+1.22V
REFERENCE
A ≈ 2.05
17k
MAX1282
+2.500V MAX1283
11 DOUT
12 SSTRB
1 VDD1
16 VDD2
10 GND
GND
CAPACITIVE
REF DAC
INPUT
CH0 MUX
CH1
CHOLD
12pF
ZERO
COMPARATOR
CH2
CH3 CSWITCH*
COM 6pF
RIN
800Ω
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
VDD1/2
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1 AND CH2/CH3.
*INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MAX1282.PDF ] | |
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