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PDF MAX1266 Data sheet ( Hoja de datos )

Número de pieza MAX1266
Descripción 12-Bit ADCs
Fabricantes Maxim Integrated 
Logotipo Maxim Integrated Logotipo



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No Preview Available ! MAX1266 Hoja de datos, Descripción, Manual

19-2722; Rev 0; 04/03
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
The MAX1266/MAX1268 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed 12-bit parallel interface. They operate with
a single +5V analog supply.
Power consumption is only 10mW at the maximum sam-
pling rate of 420ksps. Two software-selectable power-
down modes enable the MAX1266/MAX1268 to be shut
down between conversions; accessing the parallel
interface returns them to normal operation. Powering
down between conversions can reduce supply below
10µA at lower sampling rates.
Both devices offer software-configurable analog inputs for
unipolar/bipolar and single-ended/pseudo-differential
operation. In single-ended mode, the MAX1266 has six
input channels and the MAX1268 has two (three input
channels and one input channel, respectively, when in
pseudo-differential mode).
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power-consumption and space requirements. The
MAX1266 is offered in a 28-pin QSOP package, while the
MAX1268 is available in a 24-pin QSOP. For pin-compati-
ble +3V, 12-bit versions, see the MAX1265/MAX1267.
Industrial Control Systems
Energy Management
Data-Acquisition Systems
Applications
Data Logging
Patient Monitoring
Touch Screens
Ordering Information
PART
TEMP RANGE
MAX1266ACEI 0°C to +70°C
MAX1266BCEI 0°C to +70°C
MAX1266AEEI -40°C to +85°C
MAX1266BEEI -40°C to +85°C
MAX1268ACEG 0°C to +70°C
MAX1268BCEG 0°C to +70°C
MAX1268AEEG -40°C to +85°C
MAX1268BEEG -40°C to +85°C
PIN-PACKAGE
28 QSOP
28 QSOP
28 QSOP
28 QSOP
24 QSOP
24 QSOP
24 QSOP
24 QSOP
INL
(LSB)
±0.5
±1
±0.5
±1
±0.5
±1
±0.5
±1
Features
o 12-Bit Resolution, ±0.5 LSB Linearity
o Single +5V Operation
o Internal +2.5V Reference
o Software-Configurable Analog Input Multiplexer
6-Channel Single Ended/
3-Channel Pseudo-Differential (MAX1266)
2-Channel Single Ended/
1-Channel Pseudo-Differential (MAX1268)
o Software-Configurable Unipolar/Bipolar
Analog Inputs
o Low Current
2.8mA (420ksps)
1.0mA (100ksps)
400µA (10ksps)
2µA (Shutdown)
o Internal 6MHz Full-Power Bandwidth Track/Hold
o Parallel 12-Bit Interface
o Small Footprint
28-Pin QSOP (MAX1266)
24-Pin QSOP (MAX1268)
Pin Configurations
TOP VIEW
D9 1
D8 2
D7 3
D6 4
D5 5
D4 6
D3 7
D2 8
D1 9
D0 10
INT 11
RD 12
MAX1268
24 D10
23 D11
22 VDD
21 REF
20 REFADJ
19 GND
18 COM
17 CH0
16 CH1
15 CS
14 CLK
13 WR
QSOP
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX1266 pdf
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics
(VDD = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25°C, unless otherwise noted.)
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1000 2000 3000 4000 5000
DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1000 2000 3000 4000
DIGITAL OUTPUT CODE
5000
SUPPLY CURRENT vs. SAMPLE FREQUENCY
10,000
WITH INTERNAL REFERENCE
1000
100
10
0
0.1 1
WITH EXTERNAL REFERENCE
10 100 1k 10k 100k 1M
fSAMPLE (Hz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2.2
RL =
CODE = 101010100000
2.1
SUPPLY CURRENT vs. TEMPERATURE
2.3 RL =
CODE = 101010100000
2.2
2.1
STANDBY CURRENT vs. SUPPLY VOLTAGE
990
980
970
2.0 2.0 960
1.9 950
1.9
1.8 940
1.8
4.50
4.75 5.00
VDD (V)
5.25
5.50
STANDBY CURRENT vs. TEMPERATURE
990
1.7
-40
3.0
-15 10 35 60
TEMPERATURE (°C)
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
85
930
4.50
2.2
4.75 5.00 5.25
VDD (V)
POWER-DOWN CURRENT
vs. TEMPERATURE
5.50
980
2.5 2.1
970
960 2.0 2.0
950
940
930
-40
-15 10 35 60
TEMPERATURE (°C)
85
1.5
1.0
4.50
4.75 5.00
VDD (V)
5.25
5.50
1.9
1.8
-40
-15 10 35 60
TEMPERATURE (°C)
85
_______________________________________________________________________________________ 5

5 Page





MAX1266 arduino
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
tACQ = 9(RS + RIN)CIN
where RS is the source impedance of the input signal,
RIN (800) is the input resistance, and CIN (12pF) is
the ADC’s input capacitance. Source impedances
below 3khave no significant impact on the MAX1266/
MAX1268s’ AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
Input Bandwidth
The MAX1266/MAX1268 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Starting a Conversion
Initiate a conversion by writing a control byte, which
selects the multiplexer channel and configures the
MAX1266/MAX1268 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
ends (Figure 4). Note that, when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the
MAX1266/MAX1268 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Selecting Clock Mode
The MAX1266/MAX1268 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1266/MAX1268
enter the default external clock mode.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bit D7 of
the control byte must be set to 1 and bit D6 must be set
to zero. The internal clock frequency is then selected,
resulting in a conversion time of 3.6µs. When using the
internal clock mode, tie the CLK pin either high or low
to prevent the pin from floating.
______________________________________________________________________________________ 11

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