|
|
PDF MAX1138 Data sheet ( Hoja de datos )
| Número de pieza | MAX1138 | |
| Descripción | 2-Wire Serial 10-Bit ADCs | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MAX1138 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
|
No Preview Available !
19-2334; Rev 6; 3/10
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
General Description
The MAX1136–MAX1139 low-power, 10-bit, multichannel
analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply of 2.7V to 3.6V (MAX1137/
MAX1139) or 4.5V to 5.5V (MAX1136/MAX1138) and
require only 670µA at the maximum sampling rate of
94.4ksps. Supply current falls below 230µA for sampling
rates under 46ksps. AutoShutdown™ powers down the
devices between conversions, reducing supply current to
less than 1µA at low throughput rates. The
MAX1136/MAX1137 have four analog input channels
each, while the MAX1138/MAX1139 have 12 analog input
channels each. The fully differential analog inputs are
software configurable for unipolar or bipolar, and single
ended or differential operation.
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
voltage ranging from 1V to VDD. The MAX1137/
MAX1139 feature a 2.048V internal reference and the
MAX1136/MAX1138 feature a 4.096V internal reference.
The MAX1136/MAX1137 are available in an 8-pin µMAX®
package. The MAX1138/MAX1139 are available in a
16-pin QSOP package. The MAX1136–MAX1139 are
guaranteed over the extended temperature range
(-40°C to +85°C). For pin-compatible 12-bit parts, refer to
the MAX1236–MAX1239 data sheet. For pin-compatible
8-bit parts, refer to the MAX1036–MAX1039 data sheet.
Applications
Hand-Held Portable
Applications
Medical Instruments
Battery-Powered Test
Equipment
Solar-Powered Remote
Systems
Received-Signal-Strength
Indicators
System Supervision
Selector Guide
PART
INPUT
CHANNELS
INTERNAL
REFERENCE
(V)
SUPPLY
VOLTAGE
(V)
INL
(LSB)
MAX1136
MAX1137
MAX1138
MAX1139
4
4
12
12
4.096
2.048
4.096
2.048
4.5 to 5.5
2.7 to 3.6
4.5 to 5.5
2.7 to 3.6
±1
±1
±1
±1
Features
o High-Speed I2C-Compatible Serial Interface
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single-Supply
2.7V to 3.6V (MAX1137/MAX1139)
4.5V to 5.5V (MAX1136/MAX1138)
o Internal Reference
2.048V (MAX1137/MAX1139)
4.096V (MAX1136/MAX1138)
o External Reference: 1V to VDD
o Internal Clock
o 4-Channel Single-Ended or 2-Channel Fully
Differential (MAX1136/MAX1137)
o 12-Channel Single-Ended or 6-Channel Fully
Differential (MAX1138/MAX1139)
o Internal FIFO with Channel-Scan Mode
o Low Power
670µA at 94.4ksps
230µA at 40ksps
60µA at 10ksps
6µA at 1ksps
0.5µA in Power-Down Mode
o Software-Configurable Unipolar/Bipolar
o Small Packages
8-Pin µMAX (MAX1136/MAX1137)
16-Pin QSOP (MAX1138/MAX1139)
Ordering Information
PART
MAX1136EUA+
MAX1137EUA+
MAX1138EEE+
MAX1139EEE+
TEMP RANGE PIN-
I2C SLAVE
PACKAGE ADDRESS
-40°C to +85°C 8 µMAX
0110100
-40°C to +85°C 8 µMAX
0110100
-40°C to +85°C 16 QSOP 0110101
-40°C to +85°C 16 QSOP 0110101
+Denotes a lead(Pb)-free/RoHS-compliant package.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configurations and Typical Operating Circuit appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX1137/MAX1139), VDD = 4.5V to 5.5V (MAX1136/MAX1138), VREF = 2.048V (MAX1137/MAX1139), VREF =
4.096V (MAX1136/MAX1138), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See
Tables 1–5 for programming notation.).)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled)
tRCL Measured from 0.3VDD to 0.7VDD
20 80 ns
Rise Time of SCL Signal after
Acknowledge Bit
tRCL1 Measured from 0.3VDD to 0.7VDD
20 160 ns
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
tFCL
tRDA
tFDA
tSU, STO
CB
tSP
Measured from 0.3VDD to 0.7VDD
Measured from 0.3VDD to 0.7VDD
Measured from 0.3VDD to 0.7VDD (Note 11)
(Notes 10 and 13)
20
20
20
160
0
80 ns
160 ns
160 ns
ns
400 pF
10 ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
For DC accuracy, the MAX1136/MAX1138 are tested at VDD = 5V and the MAX1137/MAX1139 are tested at VDD = 3V. All
devices are configured for unipolar, single-ended inputs.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Offset nulled.
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
ADC performance is limited by the converter’s noise floor, typically 300µVP-P.
Note 9: Measured as for the MAX1137/MAX1139
[ ]⎡
⎢
⎣
VFS(3.6V) − VFS(2.7V)
×
2N −1⎤
VREF
⎥
⎦
(3.6V − 2.7V)
and for the MAX1136/MAX1138
[ ]⎡
⎢
⎣
VFS(5.5V) − VFS(4.5V)
×
2N −1⎤
VREF
⎥
⎦
(5.5V − 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 11: The minimum value is specified at +25°C.
Note 12: CB = total capacitance of one bus line in pF.
Note 13: fSCL must meet the minimum clock low time plus the rise/fall times.
_______________________________________________________________________________________ 5
5 Page 
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial 10-Bit ADCs
swing from (GND - 0.3V) to (VDD + 0.3V) without caus-
ing damage to the device. For accurate conversions
the inputs must not go more than 50mV below GND or
above VDD.
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the
MAX1136–MAX1139 analog-input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are the
difference between the analog input selected by CS[3:0]
and GND (Table 3). In differential mode (SGL/ DIF = 0) the
digital conversion results are the difference between the
“+” and the “-” analog inputs selected by CS[3:0] (Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to VREF. A negative differential analog
input in unipolar mode will cause the digital output
code to be zero. Selecting bipolar mode sets the differ-
ential input range to ±VREF/2. The digital output code is
binary in unipolar mode and two’s complement in bipo-
lar mode, see the Transfer Functions section.
In single-ended mode the MAX1136–MAX1139 will
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to VREF.
2-Wire Digital Interface
The MAX1136–MAX1139 feature a 2-wire interface con-
sisting of a serial data line (SDA) and serial clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX1136–MAX1139 and the master at
rates up to 1.7MHz. The MAX1136–MAX1139 are slaves
that transfer and receive data. The master (typically a
microcontroller) initiates data transfer on the bus and
generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit). Series resistors (RS) are optional.
They protect the input architecture of the MAX1136–
MAX1139 from high voltage spikes on the bus lines, min-
imize crosstalk, and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. A minimum of eighteen clock cycles are required
to transfer the data in or out of the MAX1136–MAX1139.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is stable are considered control signals (see the
START and STOP Conditions section). Both SDA and
SCL remain high when the bus is not busy.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see HS-mode).
S
SDA
Sr
P
SCL
Figure 5. START and STOP Conditions
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX1136–MAX1139 (slave) generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse
(Figure 6). To generate a not-acknowledge, the receiv-
er allows SDA to be pulled high before the rising edge
of the acknowledge-related clock pulse and leaves
SDA high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer the bus master should reattempt
communication at a later time.
S
SDA
SCL 1 2
Figure 6. Acknowledge Bits
NOT ACKNOWLEDGE
ACKNOWLEDGE
89
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet MAX1138.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MAX113 | +3V / 400ksps / 4/8-Channel / 8-Bit ADCs with 1UA Power-Down | Maxim Integrated |
| MAX11300 | 20-Port Programmable Mixed-Signal I/O | Maxim Integrated |
| MAX11301 | 20-Port Programmable Mixed-Signal I/O | Maxim Integrated |
| MAX11311 | 12-Port Programmable Mixed-Signal I/O | Maxim Integrated |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |