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PDF DA7211 Data sheet ( Hoja de datos )
| Número de pieza | DA7211 | |
| Descripción | Ultra-low power stereo codec | |
| Fabricantes | Dialog Semiconductor | |
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DA7211
Ultra-low power stereo codec
Company confidential
General description
DA7211 features a high fidelity and powerful 72 mW per channel headphone amplifier. The device
may be operated from a single 1.8 V supply. Total device consumption is only 2.5 mW which helps
extend music playback time for battery operated equipment.
The fully integrated fractional PLL has been designed to use minimal power while supporting a wide
range of input and output frequencies. Internal suppression circuits help maintain audio
synchronisation in the presence of system noise on the external clock.
Six analogue input pins allow multiple audio sources to be internally mixed, eliminating the need for
external switches. Both single-ended and fully-differential line and microphone inputs are supported
with built-in variable gain amplifiers to optimise the dynamic range prior to digitisation. This provides
hardware support for ambient noise cancellation.
The DA7211 provides two volume-controlled differential/single-ended stereo line-out drivers and
ground-centred stereo amplifiers to directly drive standard 3-wire 16 Ω headphones. For example the
dc coupled, dedicated pop-free drivers may be connected simultaneously to stereo headphones,
stereo speakers and a mono line out without external switches.
All filtering functions are performed digitally including 5-band EQ and a digital input AGC with
programmable attack and decay parameters. A configurable signal processing engine allows various
audio enhancements and effects such as acoustic filtering, transducer equalisation, wind noise
suppression and 3D sound
The multi-slot I2S/PCM interface supports all common sample rates between 8 and 96 kHz in master
or slave mode operation.
Key features
■ Stereo multi-bit Delta Sigma DAC with SNR ■ Audio serial data bus supports I2S,
100 dB ('A' weighted @ 48 kHz)
left/right justified, DSP and TDM modes
■ Stereo multi-bit Delta Sigma ADC with SNR ■ Stereo or mono differential microphone
96 dB ('A' weighted @ 48 kHz)
interface
■ Ultra low-power stereo headphone driver with ■ Programmable ultra-low noise bias supply for
□ Stereo DAC to HP playback power:
2.5 mW
electret microphones
■ Volume controlled stereo auxiliary inputs and
□ 2x58 mW output power (16 Ω)
outputs supporting FM Radio and fixed gain
□
□
‘Capless’ output via GND centred signals
Four level charge pump with continuous
tracking of audio signal (Class G)
■
■
speaker amplifiers
Multi-mode audio routing and mixers
Pop & click suppression circuitry
□ Short circuit protection
■ ASSP DSP filter engine for digital audio
■ Support of 8, 11.025, 12, 16, 22.05, 24, 32,
enhancements (acoustic filtering, wind noise
suppression, 5-band equaliser, 3D sound,
44.1, 48 and 96 kHz sample rates
automatic gain control)
■ On-chip PLL with signal shaper and audio ■ Supports supply from single voltage
Sample Rate Matching
(1.8/2.5 V)
■ 2-wire software control interface
■ Extensive modular power control
■ Package: 36 bump WL-CSP 3x3 – 0.5 mm
pitch
Applications
■ Personal media players
■ Portable consumer devices
■ Music handsets
■ Personal navigation devices
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
1 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
1 page  
DA7211
Ultra-low power stereo codec
Company confidential
Table 18: Start-up times after setting SC_MST_EN = 1 ..................................................................... 25
Table 19: ADC digital high pass filter specifications ........................................................................... 28
Table 20: Permitted register values for ALC_NOIS (0x85 [5:0]) ......................................................... 31
Table 21: DAC digital high pass filter specifications ........................................................................... 33
Table 22: Headphone/OUT1 amplifier gain settings ........................................................................... 36
Table 23: GP filter section enable bits................................................................................................. 39
Table 24: Band-equaliser corner frequencies ..................................................................................... 40
Table 25: 5-band-equaliser turn-over/centre frequencies ................................................................... 40
Table 26: Voice mode recording high pass filter specifications .......................................................... 45
Table 27: Voice mode playback high-pass filter specifications ........................................................... 47
Table 28: Internal system clock frequency .......................................................................................... 52
Table 29: Block enable and system standby bits ................................................................................ 52
Table 30: ADC and DAC clock frequencies ........................................................................................ 53
Table 31: Master mode PLL-DIV look up table ................................................................................... 54
Table 32: SRM mode PLL-DIV look up table ...................................................................................... 54
Table 33: PLL master mode register setting recommendations.......................................................... 55
Table 34: MCLK frequencies in non-PLL slave mode......................................................................... 57
Table 35: Non-PLL slave mode and PLL master mode sample rate settings ..................................... 58
Table 36: SRM mode PLL division ratio settings ................................................................................ 60
Table 37: Slave mode PLL-enabled register setting recommendations ............................................. 60
Table 38: Register map ....................................................................................................................... 65
Table 39: CONTROL 0x01 .................................................................................................................. 68
Table 40: STATUS 0x02...................................................................................................................... 68
Table 41: STARTUP 1 0x03 ................................................................................................................ 69
Table 42: STARTUP 2 0x04 ................................................................................................................ 69
Table 43: STARTUP 3 0x05 ................................................................................................................ 70
Table 44: MIC_L 0x07 ......................................................................................................................... 70
Table 45: MIC_R 0x08......................................................................................................................... 71
Table 46: AUX1_L 0x09 ...................................................................................................................... 71
Table 47: AUX1_R 0x0A ..................................................................................................................... 71
Table 48: IN_GAIN 0x0C..................................................................................................................... 72
Table 49: INMIX_L 0x0D ..................................................................................................................... 73
Table 50: INMIX_R 0x0E..................................................................................................................... 73
Table 51: ADC_HPF 0x0F................................................................................................................... 74
Table 52: ADC 0x10 ............................................................................................................................ 74
Table 53: ADC_EQ1_2 0x11 ............................................................................................................... 75
Table 54: ADC_EQ3_4 0x12 ............................................................................................................... 76
Table 55: ADC_EQ5 0x13 ................................................................................................................... 77
Table 56: DAC_HPF 0x14 ................................................................................................................... 78
Table 57: DAC_L 0x15 ........................................................................................................................ 78
Table 58: DAC_R 0x16........................................................................................................................ 79
Table 59: DAC_SEL 0x17 ................................................................................................................... 79
Table 60: SOFTMUTE 0x18 ................................................................................................................ 80
Table 61: DAC_EQ1_2 0x19 ............................................................................................................... 81
Table 62: DAC_EQ3_4 0x1A .............................................................................................................. 82
Table 63: DAC_EQ5 0x1B................................................................................................................... 83
Table 64: OUTMIX_L 0x1C ................................................................................................................. 83
Table 65: OUTMIX_R 0x1D................................................................................................................. 84
Table 66: OUT1_L 0x1E...................................................................................................................... 84
Table 67: OUT1_R 0x1F ..................................................................................................................... 85
Table 68: HP_L_VOL 0x21.................................................................................................................. 85
Table 69: HP_R_VOL 0x22 ................................................................................................................. 86
Table 70: HP_CFG 0x23 ..................................................................................................................... 86
Table 71: ZEROX 0x24 ....................................................................................................................... 86
Table 72: DAI_SRC_SEL 0x25 ........................................................................................................... 87
Table 73: DAI_CFG1 0x26 .................................................................................................................. 87
Table 74: DAI_CFG2 0x27 .................................................................................................................. 87
Table 75: DAI_CFG3 0x28 .................................................................................................................. 88
Table 76: PLL_DIV1 0x29 ................................................................................................................... 88
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
5 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
5 Page 
DA7211
Ultra-low power stereo codec
Company confidential
Pin no. Pin name
5E DATOUT
5F SK
4F SI
3E CLK
3F WCLK
2F VDDCP
1F HPCF1P
1E HPCF1N
2E GNDCP
1D HPCF2P
2D HPCF2N
1C HPCSN
2C HPCSP
1B HPL
1A HPR
4E GND
3A DACREF
2A OUT1P_R
4A OUT1N_R
2B OUT1P_L
3B OUT1N_L
4B ADCREF
5B VMID
6A VBG
Description
I2S digital data output
Digital clock for 2-wire
2-wire input and open drain output
Digital bit clock for I2S
Digital word clock for I2S
Headphone charge pump supply
Head phone amp charge pump floating cap1 +ve
Head phone amp charge pump floating cap1 –ve
Headphone and digital ground
Head phone amp charge pump floating cap2 +ve
Head phone amp charge pump floating cap2 –ve
Head phone amp charge pump storage cap –ve
Head phone amp charge pump storage cap +ve
Left head phone amp output
Right head phone amp output
Ground bump
Decoupling capacitor for DAC
Differential or single ended +ve line out right
Differential –ve line out right
Differential or single ended +ve line out left
Differential –ve line out left
Decoupling capacitor for ADC
Decoupling capacitor for VMID
Decoupling capacitor for VBG
Datasheet
CFR0011-120-00 Rev 5
Revision 3e
11 of 105
15-Oct-2015
© 2015 Dialog Semiconductor
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DA7211.PDF ] | |
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