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PDF IDT74ALVC16244A Data sheet ( Hoja de datos )
| Número de pieza | IDT74ALVC16244A | |
| Descripción | 3.3V CMOS 16-BIT BUFFER/DRIVER | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
3.3V CMOS 16-BIT
BUFFER/DRIVER WITH
3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
IDT74ALVC16244A
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DESCRIPTION:
This 16-bit buffer/driver is built using advanced dual metal CMOS
technology. The ALVC16244A is designed specifically to improve the
performance and density of 3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters. The device can be used as
four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true
outputs and symmetrical active-low output-enable (OE) inputs.
The ALVC16244A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1OE 1
1A1 47
1A2 46
1A3 44
1A4 43
2 1Y1
3 1Y2
5 1Y3
6 1Y4
3OE 25
3A1 36
3A2 35
3A3 33
32
3A4
2OE 48
2A1 41
8 2Y1
2A2 40
2A3 38
2A4 37
9 2Y2
11 2Y3
12 2Y4
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
©2016 Integrated Device Technology, Inc.
1
4OE 24
4A1 30
4A2 29
4A3 27
4A4 26
13 3Y1
14 3Y2
16 3Y3
17 3Y4
19 4Y1
20 4Y2
22 4Y3
23 4Y4
JUNE 2016
DSC-4698/7
1 page  
IDT74ALVC16244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VLOAD
6
6
VIH 2.7
2.7
VT 1.5
1.5
VLZ 300
300
VHZ 300
300
CL 50
50
VCC(2)= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
Propagation Delay
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
ALVC Link
Pulse(1, 2)
Generator
VIN
VCC
VOUT
D.U.T.
500Ω
VLOAD
Open
GND
RT
500Ω
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
VLOAD
GND
Open
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
CONTROL
INPUT
ENABLE
tPZL
DISABLE
tPLZ
VIH
VT
0V
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VLOAD/2
VT
tPHZ
VT
0V
VLOAD/2
VOL + VLZ
VOL
VOH
VOH - VHZ
0V
ALVC Link
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
tSU tH
tREM
SYNCHRONOUS
CONTROL
tSU tH
Set-up, Hold, and Release Times
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
ALVC Link
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
Pulse Width
VT
VT
ALVC Link
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT74ALVC16244A.PDF ] | |
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