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PDF GS881Z32CD Data sheet ( Hoja de datos )

Número de pieza GS881Z32CD
Descripción 9Mb Pipelined and Flow Through Synchronous NBT SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS881Z32CD Hoja de datos, Descripción, Manual

GS881Z18/32/36C(T/D)-xxx
100-Pin TQFP & 165-Bump BGA 9Mb Pipelined and Flow Through
Commercial Temp
Synchronous NBT SRAM
333 MHz–150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 18M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard packages
• RoHS-compliant 100-lead TQFP and 165-bump BGA
packages available
Functional Description
The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D)
is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS881Z18C(T/D)/GS881Z32C(T/D)/GS881Z36C(T/D)
is implemented with GSI's high performance CMOS
technology and is available in a JEDEC-standard 100-pin
TQFP package.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-333 -300 -250 -200 -150 Unit
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
2.5 2.5 2.5 3.0 3.8 ns
3.0 3.3 4.0 5.0 6.7 ns
240 225 195 170 140 mA
280 260 225 195 160 mA
4.5 5.0 5.5 6.5 7.5 ns
4.5 5.0 5.5 6.5 7.5 ns
180 165 160 140 128 mA
205 190 180 160 145 mA
Rev: 1.04 7/2012
1/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS881Z32CD pdf
100-Pin TQFP Pin Descriptions
Symbol
A0, A1
A
CK
BA
BB
BC
BD
W
E1
E2
E3
G
ADV
CKE
NC
DQA
DQB
DQC
DQD
DQPA
DQPB
DQPC
DQPD
ZZ
FT
LBO
VDD
VSS
VDDQ
Type
In
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
In
In
In
In
In
In
GS881Z18/32/36C(T/D)-xxx
Description
Burst Address Inputs; Preload the burst counter
Address Inputs
Clock Input Signal
Byte Write signal for data inputs DQA; active low
Byte Write signal for data inputs DQB; active low
Byte Write signal for data inputs DQC; active low
Byte Write signal for data inputs DQD; active low
Write Enable; active low
Chip Enable; active low
Chip Enable—Active High. For self decoded depth expansion
Chip Enable—Active Low. For self decoded depth expansion
Output Enable; active low
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
No Connect
Byte A Data Input and Output pins
Byte B Data Input and Output pins
Byte C Data Input and Output pins
Byte D Data Input and Output pins
9th Data I/O Pin; Byte A
9th Data I/O Pin; Byte B
9th Data I/O Pin; Byte C
9th Data I/O Pin; Byte D
Power down control; active high
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low.
Core power supply
Ground
Output driver power supply
Rev: 1.04 7/2012
5/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS881Z32CD arduino
GS881Z18/32/36C(T/D)-xxx
GS881Z18/32/36C NBT SRAM Functional Block Diagram
Rev: 1.04 7/2012
11/38
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

11 Page







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