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PDF GS8672T38BGE Data sheet ( Hoja de datos )

Número de pieza GS8672T38BGE
Descripción 72Mb SigmaDDR-II+ Burst of 2 ECCRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8672T38BGE Hoja de datos, Descripción, Manual

GS8672T20/38BE-633/550/500/450/400
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-II+TM
Burst of 2 ECCRAMTM
633 MHz–400 MHz
1.8 V VDD
1.5 V I/O
Features
• 2.5 Clock Latency
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard package
• Double Data Rate interface
• Byte Write capability
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (DQ), Byte Write (BW),
and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 36Mb and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRECCRAM Overview
The GS8672T20/38BE SigmaDDR-II+ ECCRAMs are built in
compliance with the SigmaDDR-II+ SRAM pinout standard
for Common I/O synchronous SRAMs. They are
75,497,472-bit (72Mb) SRAMs. The GS8672T20/38BE
SigmaDDR SRAMs are just one element in a family of low
power, low voltage HSTL I/O SRAMs designed to operate at
the speeds needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS8672T20/38BE SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaDDR-II+ B2 ECCRAM is always one address
pin less than the advertised index depth (e.g., the 4M x 18 has
an 2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
tKHKH
tKHQV
-633
1.57 ns
0.45 ns
Parameter Synopsis
-550
1.81 ns
0.45 ns
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
Rev: 1.02a 6/2013
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS8672T38BGE pdf
GS8672T20/38BE-633/550/500/450/400
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II+ ECCRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs
are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are burst operations. In every case where a read or write command is accepted by the ECCRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,
if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the ECCRAM on the next cycle after a read command captured by the ECCRAM, the device will complete the two beat read data
transfer and then execute the deselect command, returning the output drivers to High-Z. A high on the LD pin prevents the RAM
from loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst
transfer operations.
SigmaDDR-II+ B2 ECCRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.
SigmaDDR-II+ B2 ECCRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The ECCRAM executes Late write data
transfers. Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write
command (LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the
ECCRAM captures data in on the next rising edge of K, for a total of two transfers per address load.
Rev: 1.02a 6/2013
5/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS8672T38BGE arduino
GS8672T20/38BE-633/550/500/450/400
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
–0.5 to 2.4
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O Voltage on I/O Pins
–0.5 to VDDQ +0.5 (2.4 V max.)
V
VIN Voltage on Other Input Pins
–0.5 to VDDQ +0.5 (2.4 V max.)
V
IIN Input Current on Any Pin
+/–100
mA dc
IOUT Output Current on Any I/O Pin
+/–100
mA dc
TJ Maximum Junction Temperature
125 oC
TSTG Storage Temperature
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min. Typ. Max. Unit
Supply Voltage
VDD
1.7
1.8 1.9
V
I/O Supply Voltage
VDDQ
1.4 — 1.6 V
Reference Voltage
VREF
VDDQ/2 – 0.05
— VDDQ/2 + 0.05 V
Note:.
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter
Symbol
Min. Typ. Max. Unit
Junction Temperature
(Commercial Range Versions)
TJ
0 25 85 C
Junction Temperature
(Industrial Range Versions)*
TJ
–40 25 100 C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.02a 6/2013
11/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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