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PDF GS8321Z32E-V Data sheet ( Hoja de datos )

Número de pieza GS8321Z32E-V
Descripción 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8321Z32E-V Hoja de datos, Descripción, Manual

GS8321Z18/32/36E-xxxV
165-Bump FP-BGA
Commercial Temp
Industrial Temp
36Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz–133 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 18Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
The GS8321Z18/32/36E-xxxV is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8321Z18/32/36E-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8321Z18/32/36E-xxxV is implemented with GSI's high
performance CMOS technology and is available in JEDEC-
standard 165-bump FP-BGA package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline
tKQ
tCycle
3.0 3.0 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3-1-1-1 Curr (x18) 285 265 245 220 210 185 mA
Curr (x32/x36) 350 320 295 260 240 215 mA
Flow
Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x32/x36)
6.5
6.5
205
235
7.0
7.0
195
225
7.5
7.5
185
210
8.0
8.0
175
200
8.5
8.5
165
190
8.5
8.5
155
175
ns
ns
mA
mA
Rev: 1.05 6/2006
1/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

1 page




GS8321Z32E-V pdf
GS8321Z18/32/36E-xxxV
GS8321Z18/32/36E-xxxV 165-Bump BGA Pin Description
Symbol
A0, A1
An
DQA
DQB
DQC
DQD
BA, BB, BC, BD
NC
CK
CKE
W
E1
E3
E2
FT
G
ADV
ZZ
LBO
TMS
TDI
TDO
TCK
MCH
VDD
VSS
VDDQ
Type
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs
Address Inputs
Data Input and Output pins
Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low
No Connect
Clock Input Signal; active high
Clock Enable; active low
Write Enable; active low
Chip Enable; active low
Chip Enable; active low
Chip Enable; active high
Flow Through / Pipeline Mode Control
Output Enable; active low
Burst address counter advance enable; active high
Sleep mode control; active high
Linear Burst Order mode; active low
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Must Connect High
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 1.05 6/2006
5/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

5 Page





GS8321Z32E-V arduino
GS8321Z18/32/36E-xxxV
Flow Through Mode Data I/O State Diagram
BW
High Z
(Data In)
R
D
WR
High Z
B
D
RB
Data Out
W (Q Valid)
D
Key
Input Command Code
ƒ Transition
Current State (n)
Next State (n+1)
n n+1
Clock (CK)
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
n+2 n+3
Command
ƒƒƒƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow through Read Write Control State Diagram
Rev: 1.05 6/2006
11/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology

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