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PDF GS8320Z18T Data sheet ( Hoja de datos )

Número de pieza GS8320Z18T
Descripción 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8320Z18T Hoja de datos, Descripción, Manual

100-Pin TQFP
Commercial Temp
Industrial Temp
Product Preview
GS8320Z18/36T-250/225/200/166/150/133
36Mb Pipelined and Flow Through 250 MHz133 MHz
Synchronous NBT SRAM
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
Functional Description
• NBT (No Bus Turn Around) functionality allows zero wait
The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
read-write-read bus utilization; Fully pin-compatible with
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
both pipelined and flow through NtRAM™, NoBL™ and
pipelined read/double late write or flow through read/single
ZBT™ SRAMs
late write SRAMs, allow utilization of all available bus
• 2.5 V or 3.3 V +10%/5% core power supply
bandwidth by eliminating the need to insert deselect cycles
• 2.5 V or 3.3 V I/O supply
when the device is switched from read to write cycles.
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.3 2.5 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3.3 V
Curr (x18) 365 335 300 265 240 220 mA
Curr (x32/x36) 430 390 350 305 280 245 mA
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36T may be configured by the user to operate
2.5 V
Curr (x18) 360 330 295 260 235 215 mA
Curr (x32/x36) 420 380 340 295 270 235 mA
Flow
Through
2-1-1-1
tKQ
tCycle
6.0 6.5 7.5 8.5 10 11 ns
7.0 7.5 8.5 10 10 15 ns
3.3 V
Curr (x18) 200 200 180 180 180 135 mA
Curr (x32/x36) 230 230 195 195 195 145 mA
2.5 V
Curr (x18) 200 200 180 180 180 130 mA
Curr (x32/x36) 225 225 195 195 195 145 mA
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
BC
DE
F
Read/Write
R
WR
W
R
W
Flow Through
Data I/O
Pipelined
Data I/O
QA DB QC DD QE
QA DB QC DD QE
Rev: 1.01 10/2001
1/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

1 page




GS8320Z18T pdf
GS8320Z18/36 NBT SRAM Functional Block Diagram
Product Preview
GS8320Z18/36T-250/225/200/166/150/133
Rev: 1.01 10/2001
5/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

5 Page





GS8320Z18T arduino
Product Preview
GS8320Z18/36T-250/225/200/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Output Register Control
FT
L
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Note:
There pull-up device on the and FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note: The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Rev: 1.01 10/2001
11/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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