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PDF GS82582TT20GE Data sheet ( Hoja de datos )

Número de pieza GS82582TT20GE
Descripción 288Mb SigmaDDR-II+ Burst of 2 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS82582TT20GE Hoja de datos, Descripción, Manual

GS82582TT20/38GE-550/500/450/400
165-Bump BGA
Commercial Temp
Industrial Temp
288Mb SigmaDDR-II+TM
Burst of 2 SRAM
550 MHz–400 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaDDRTM Interface
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• RoHS-compliant 165-bump BGA package
SigmaDDR-IIFamily Overview
The GS82582TT20/38GE are built in compliance with the
SigmaDDR-II+ SRAM pinout standard for Common I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582TT20/38GE SigmaDDR-II+ SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS82582TT20/38GE SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore, the address field of a
SigmaDDR-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 16M x 18 has an 8M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-550
1.81 ns
0.45 ns
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
Rev: 1.03 4/2016
1/24
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

1 page




GS82582TT20GE pdf
GS82582TT20/38GE-550/500/450/400
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "Burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,
if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to High-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaDDR-II+ Burst of 2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.
SigmaDDR-II+ Burst of 2 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Resulting Write Operation
Byte 1
D0–D8
Written
Beat 1
Byte 2
D9–D17
Unchanged
Byte 3
D0–D8
Unchanged
Beat 2
Byte 4
D9–D17
Written
Rev: 1.03 4/2016
5/24
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

5 Page





GS82582TT20GE arduino
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter
Input Capacitance
Output Capacitance
Clock Capacitance
Note:
This parameter is sample tested.
Symbol
CIN
COUT
CCLK
GS82582TT20/38GE-550/500/450/400
Test conditions
VIN = 0 V
VOUT = 0 V
VIN = 0 V
Typ. Max. Unit
4 5 pF
6 7 pF
5 6 pF
AC Test Conditions
Parameter
Input high level
Input low level
Max. input slew rate
Input reference level
Output reference level
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
Conditions
1.25 V
0.25 V
2 V/ns
0.75 V
VDDQ/2
AC Test Load Diagram
DQ
RQ = 250 (HSTL I/O)
50VREF = 0.75 V
VT = VDDQ/2
Input and Output Leakage Characteristics
Parameter
Input Leakage Current
(except mode pins)
Doff
ODT
Symbol
IIL
IILDOFF
IILODT
Output Leakage Current
IOL
Test Conditions
VIN = 0 to VDD
VIN = 0 to VDD
VIN = 0 to VDD
Output Disable,
VOUT = 0 to VDDQ
Min.
–2 uA
–20 uA
–2 uA
–2 uA
Max
2 uA
2 uA
20 uA
2 uA
Rev: 1.03 4/2016
11/24
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology

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