|
|
PDF GS8182Q18D Data sheet ( Hoja de datos )
| Número de pieza | GS8182Q18D | |
| Descripción | 18Mb Burst of 2 SigmaQuad-II SRAM | |
| Fabricantes | GSI Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de GS8182Q18D (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
|
No Preview Available !
Preliminary
GS8182Q18D-200/167/133
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
SigmaQuad-II SRAM
200MHz–133MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
SigmaRAM™ Family Overview
GS8182Q18 are built in compliance with the SigmaQuad-II
SRAM pinout standard for Separate I/O synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage HSTL I/O SRAMs designed
to operate at the speeds needed to implement economical high
performance networking systems.
Clocking and Addressing Schemes
A Burst of 2 SigmaQuad-II SRAM is a synchronous device. It
employs two input register clock inputs, K and K. K and K are
independent single-ended clock inputs, not differential inputs
to a single differential clock input buffer. The device also
allows the user to manipulate the output register clock inputs
quasi independently with the C and C clock inputs. C and C are
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
also independent single-ended clock inputs, not differential
inputs. If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
tKHKH
tKHQV
Parameter Synopsis
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
-133
7.5 ns
0.5 ns
Rev: 1.02 11/2004
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
1 page  
Preliminary
GS8182Q18D-200/167/133
SigmaQuad-II B2 SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied
high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the
Read Enable-bar pin, R, begins a read port deselect cycle.
Burst of 2 Double Data Rate SigmaQuad-II SRAM Read First
Read A
NOP
Write B
Read C Write D Read E Write F Read G Write H NOP
K
K
Address
R
W
BWx
D
C
C
Q
CQ
CQ
A
BC
DE
FG
H
B B+1 D D+1 F F+1 H H+1
A A+1
C C+1 E E+1 G
Rev: 1.02 11/2004
5/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
5 Page 
Separate I/O Burst of 2 SigmaQuad-II SRAM Read Truth Table
AR
Output Next State
K↑ K↑
(tn) (tn)
K↑
(tn)
X1
Deselect
V0
Read
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Preliminary
GS8182Q18D-200/167/133
Q
K↑
(tn+1)
Hi-Z
Q0
Q
K↑
(tn+1½)
Hi-Z
Q1
Separate I/O Burst of 2 SigmaQuad-II SRAM Write Truth Table
A W BWn BWn
Input Next State
K↑
(tn + ½)
K↑
(tn)
K↑ K↑
(tn) (tn + ½)
K ↑, K ↑
(tn), (tn + ½)
V000
Write Byte Dx0, Write Byte Dx1
V001
Write Byte Dx0, Write Abort Byte Dx1
V010
Write Abort Byte Dx0, Write Byte Dx1
X 0 1 1 Write Abort Byte Dx0, Write Abort Byte Dx1
X1XX
Deselect
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1
11
01
10
00
D0–D8
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
D
K↑
(tn)
D0
D0
X
X
X
D
K↑
(tn + ½)
D1
X
D1
X
X
Rev: 1.02 11/2004
11/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet GS8182Q18D.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| GS8182Q18D | 18Mb Burst of 2 SigmaQuad-II SRAM | GSI Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |