PDF GS8182D18D Data sheet ( Hoja de datos )

Número de pieza	GS8182D18D
Descripción	18Mb Burst of 4 SigmaQuad-II SRAM
Fabricantes	GSI Technology
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No Preview Available ! Preliminary GS8182D18D-250/200/167 165-Bump BGA Commercial Temp Industrial Temp 18Mb Burst of 4 SigmaQuad-II SRAM 250 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • 1.8 V +150/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices SigmaRAM™ Family Overview GS8182D18 are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 4 SigmaQuad-II SRAM is a synchronous device. It employs two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are Bottom View 165-Bump, 13 mm x 15 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O Burst of 4 RAMs always transfer data in four packets, A0 and A1 are internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfers. Because the LSBs are tied off internally, the address field of a Burst of 4 RAM is always two address pins less than the advertised index depth (e.g., the 1M x 18 has a 256K addressable index). Parameter Synopsis tKHKH tKHQV -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.50 ns Rev: 1.02 11/2004 1/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 1 page Preliminary GS8182D18D-250/200/167 SigmaQuad-II B4 SRAM DDR Read The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), after the following rising edge of K with a rising edge of C (or by K if C and C are tied high), after the next rising edge of K with a rising edge of C, and after the following rising edge of K with a rising edge of C. Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle. Burst of 4 Double Data Rate SigmaQuad-II SRAM Read First Read A NOP Read B Write C Read D Write E NOP K K Address R W BWx D C C Q CQ CQ A BCDE C C+1 C+2 C+3 E E+1 A A+1 A+2 A+3 B B+1 B+2 B+3 D D+1 D+2 Rev: 1.02 11/2004 5/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 5 Page State Diagram Power-Up Preliminary GS8182D18D-250/200/167 READ R Count = 2 Read NOP READ READ Load New Read Address R Count = 0 Always READ R Count = 2 DDR Read R Count = R Count + 1 READ R Count = 1 Always Increment Read Address WRITE Write NOP WRITE Load New Write Address W Count = 0 Always WRITE W Count = 2 DDR Write W Count = W Count + 1 WRITE W Count = 2 Always WRITE W Count = 1 Increment Write Address Notes: 1. Internal burst counter is fixed as 2-bit linear (i.e., when first address is A0+), next internal burst address is A0+1. 2. “READ” refers to read active status with R = Low, “READ” refers to read inactive status with R = High. The same is true for “WRITE” and “WRITE”. 3. Read and write state machine can be active simultaneously. 4. State machine control timing sequence is controlled by K. 5. R Count is the read counter; Burst of 4 must complete 2 DDR reads. 6. W Count is the write counter; Burst of 4 must complete 2 DDR writes. Rev: 1.02 11/2004 11/27 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2003, GSI Technology 11 Page

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