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PDF GS4288C09GL Data sheet ( Hoja de datos )

Número de pieza GS4288C09GL
Descripción 288Mb CIO Low Latency DRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS4288C09GL Hoja de datos, Descripción, Manual

GS4288C09/18/36L
144-Ball BGA
Commercial Temp
Industrial Temp
32M x 9, 16M x 18, 8M x 36
288Mb CIO Low Latency DRAM (LLDRAM) II
533 MHz300 MHz
2.5 V VEXT
1.8 V VDD
1.5 V or 1.8 V VDDQ
Features
• Pin- and function-compatible with Micron RLDRAM® II
• 533 MHz DDR operation (1.067Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• 8M x 36, 16M x 18, and 32M x 9 organizations available
• 8 internal banks for concurrent operation and maximum
bandwidth
• Reduced cycle time (15 ns at 533 MHz)
• Address Multiplexing (Nonmultiplexed address option
available)
• SRAM-type interface
• Programmable Read Latency (RL), row cycle time, and burst
sequence length
• Balanced Read and Write Latencies in order to optimize data
bus utilization
• Data mask for Write commands
• Differential input clocks (CK, CK)
• Differential input data clocks (DKx, DKx)
• On-chip DLL generates CK edge-aligned data and output
data clock signals
• Data valid signal (QVLD)
• 32 ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32 ms)
• 144-ball BGA package
• HSTL I/O (1.5 V or 1.8 V nominal)
• 25–60matched impedance outputs
• 2.5 V VEXT, 1.8 V VDD, 1.5 V or 1.8 V VDDQ I/O
• On-die termination (ODT) RTT
• Commerical and Industrial Temperature
Commercial (+0° TC +95°C)
Industrial (–40° TC +95°C)
Introduction
The GSI Technology 288Mb Low Latency DRAM
(LLDRAM) II is a high speed memory device designed for
high address rate data processing typically found in networking
and telecommunications applications. The 8-bank architecture
and low tRC allows access rates formerly only found in
SRAMs.
The Double Data Rate (DDR) I/O interface provides high
bandwidth data transfers, clocking out two beats of data per
clock cycle at the I/O balls. Source-synchronous clocking can
be implemented on the host device with the provided free-
running data output clock.
Commands, addresses, and control signals are single data rate
signals clocked in by the True differential input clock
transition, while input data is clocked in on both crossings of
the input data clock(s).
Read and Write data transfers always in short bursts. The burst
length is programmable to 2, 4 or 8 by setting the Mode
Register.
The device is supplied with 2.5 V VEXT and 1.8 V VDD for the
core, and 1.5 V or 1.8 V for the HSTL output drivers.
Internally generated row addresses facilitate bank-scheduled
refresh.
The device is delivered in an efficent BGA 144-ball package.
Rev: 1.03 7/2014
1/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS4288C09GL pdf
GS4288C09/18/36L
Ball Descriptions
Symbol
A0–A20
BA0–B2
CK, CK
CS
DQ0–DQ35
DK, DK
DM
TCK
TMS, TDI
WE, REF
VREF
ZQ
QKx, QKx
Type Description
Address Inputs—A0–A20 define the row and column addresses for Read and Write Operations. During
Input a Mode Register Set (MRS), the address inputs define the register settings. They are sampled at the
rising edge of CK.
Input Bank Address inputs—Select to which internal bank a command is being applied.
Input
Input Clock—CK and CK are differential input clocks. Addresses and commands are latched on the
rising edge of CK. CK is ideally 180º out of phase with CK.
Input
Chip Select—CS enables the command decoder when Low and disables it when High. When the
command decoder is disabled, new commands are ignored, but internal operations continue.
Input
Data Input—The DQ signals form the 36-bit data bus. During Read commands, the data is referenced to
both edges of QKx. During Write commands, the data is sampled at both edges of DK.
Input Data Clock—DK and DK are the differential input data clocks. All input data is referenced to both
Input
edges of DK. DK is ideally 180º out of phase with DK. For the x36 device, DQ0– DQ17 are referenced to
DK0 and DK0 and DQ18–DQ35 are referenced to DK1 and DK1. For the x9 and x18 devices, all DQs
are referenced to DK and DK. All DKx and DKx pins must always be supplied to the device.
Input Data Mask—The DM signal is the input mask signal for Write data. Input data is masked when DM
Input is sampled High. DM is sampled on both edges of DK (DK1 for the x36 configuration). Tie signal to
ground if not used.
Input IEEE 1149.1 clock input—This ball must be tied to VSS if the JTAG function is not used.
Input IEEE 1149.1 test inputs—These balls may be left as no connects if the JTAG function is not used.
Input
Command Inputs—Sampled at the positive edge of CK, WE and REF define (together with CS) the
command to be executed.
Input Input Reference Voltage—Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Reference
External Impedance (25–60)—This signal is used to tune the device outputs to the system data bus
impedance. DQ output impedance is set to 0.2 * RQ, where RQ is a resistor from this signal to ground.
Connecting ZQ to GND invokes the Minimum Impedance mode. Connecting ZQ to VDD invokes the
Maximum Impedance mode. Refer to the Mode Register Definition diagrams (Mode Register Bit 8 (M8))
to activate or deactivate this function.
Output
Output Data Clocks—QKx and QKx are opposite polarity, output data clocks. They are free running,
and during Reads, are edge-aligned with data output from the LLDRAM II. QKx is ideally 180º out of
phase with QKx. For the x36 device, QK0 and QK0 are aligned with DQ0–DQ17, and QK1 and QK1 are
aligned with DQ18–DQ35. For the x18 device, QK0 and QK0 are aligned with DQ0–DQ8, while QK1 and
QK1 are aligned with Q9–Q17. For the x9 device, all DQs are aligned with QK0 and QK0.
Rev: 1.03 7/2014
5/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS4288C09GL arduino
GS4288C09/18/36L
On–Die Termination (ODT)
Mode Register Bit 9 (M9) set to 1 during an MRS command enables ODT. With ODT on, the DQs and DM are terminated to VTT
with a resistance, RTT. Command, address, QVLD, and clock signals are not terminated. The diagram below shows the equivalent
circuit of a DQ receiver with ODT. When a tri-stated DQ begins to drive, the ODT function is briefly switched off. When a DQ
stops driving at the end of a data transfer, ODT is switched back on. Two-state DM pin never deactivates ODT.
On–Die Termination DC Parameters
Description
Symbol
Min
Max
Termination Voltage
VTT
0.95 * VREF
1.05 * VREF
On–Die Termination
RTT
125
185
Notes:
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
On–Die Termination–Equivalent Circuit
Units
V
Notes
1, 2
3
VTT
SW
RTT
Receiver
DQ
VREF
Rev: 1.03 7/2014
11/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

11 Page







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