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PDF GS8672D37BE Data sheet ( Hoja de datos )

Número de pieza GS8672D37BE
Descripción 72Mb SigmaQuad-II+ Burst of 4 ECCRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8672D37BE Hoja de datos, Descripción, Manual

GS8672D19/37BE-450/400/375/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaQuadTM-II+
Burst of 4 ECCRAMTM
450 MHz–300 MHz
1.8 V VDD
1.5 V I/O
Features
• 2.0 Clock Latency
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write Capability due to ECC
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 18Mb, 36Mb and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadECCRAM Overview
The GS8672D19/37BE are built in compliance with the
SigmaQuad-II+ ECCRAM pinout standard for Separate I/O
synchronous ECCRAMs. They are 75,497,472-bit (72Mb)
ECCRAMs. The GS8672D19/37BE SigmaQuad ECCRAMs
are just one element in a family of low power, low voltage
HSTL I/O ECCRAMs designed to operate at the speeds needed
to implement economical high performance networking
systems.
Clocking and Addressing Schemes
The GS8672D19/37BE SigmaQuad-II+ ECCRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 ECCRAM is always two address
pins less than the advertised index depth (e.g., the 4M x18 has
a 1M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable ECCRAMs with no On-Chip
ECC, which typically have an SER of 200 FITs/Mb or more.
SER quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
tKHKH
tKHQV
-450
2.2 ns
0.45 ns
Parameter Synopsis
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.02a 6/2013
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS8672D37BE pdf
GS8672D19/37BE-450/400/375/333/300
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimized for alternating reads and writes. Separate
I/O SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers
from Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II+ B4 ECCRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Read Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command.
Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle.
SigmaQuad-II+ B4 ECCRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A low on
the Write Enable-bar pin, W, and a high on the Read Enable-bar pin, R, begins a write cycle. W is always ignored if the previous
command was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge
of K, and finally by the next rising edge of K. and by the rising edge of the K that follows.
Rev: 1.02a 6/2013
5/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS8672D37BE arduino
x36 Byte Write Enable (BWn) Truth Table
BW0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
BW1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
BW2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
BW3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
Don’t Care
Data In
GS8672D19/37BE-450/400/375/333/300
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
Don’t Care
Don’t Care
Data In
Data In
D18–D26
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
D27–D35
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Data In
Data In
Data In
Data In
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0 BW1
11
01
10
00
D0–D8
Don’t Care
Data In
Don’t Care
Data In
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.02a 6/2013
11/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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