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PDF GS8662QT07BGD Data sheet ( Hoja de datos )

Número de pieza GS8662QT07BGD
Descripción 72Mb SigmaQuad-II+ Burst of 2 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8662QT07BGD Hoja de datos, Descripción, Manual

GS8662QT07/10/19/37BD-357/333/300/250/200
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaQuad-II+TM
Burst of 2 SRAM
357 MHz–200 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS8662QT07/10/19/37BD are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662QT07/10/19/37BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662QT07/10/19/37BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II+ B2 RAM is always one address pin less than
the advertised index depth (e.g., the 8M x 8 has an 4M
addressable index).
Parameter Synopsis
tKHKH
tKHQV
-357
2.8 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
Rev: 1.00a 11/2011
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS8662QT07BGD pdf
GS8662QT07/10/19/37BD-357/333/300/250/200
2M x 36 SigmaQuad-II+ SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
NC/SA
(288Mb )
SA
W BW2 K BW1 R
SA
NC/SA
(144Mb)
CQ
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30 Q21 D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
D1
P
Q35 D35 Q26
SA
SA QVLD SA
SA
Q9
D0
Q0
R
TDO TCK
SA
SA
SA ODT SA
SA
SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
3. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
4. Pins A2 and A10 are the expansion addresses.
Rev: 1.00a 11/2011
5/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS8662QT07BGD arduino
GS8662QT07/10/19/37BD-357/333/300/250/200
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O Voltage on I/O Pins
–0.5 to VDDQ +0.5 (2.9 V max.)
V
VIN Input Voltage (Address, Control, Data, Clock)
–0.5 to VDDQ +0.5 (2.9 V max.)
V
VTIN Input Voltage (TCK, TMS, TDI)
–0.5 to VDDQ +0.5 (2.9 V max.)
V
IIN Input Current on Any Pin
+/–100
mA dc
IOUT Output Current on Any I/O Pin
+/–100
mA dc
TJ Maximum Junction Temperature
125 oC
TSTG Storage Temperature
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min. Typ. Max. Unit
Supply Voltage
VDD 1.7 1.8 1.9 V
I/O Supply Voltage
VDDQ
1.4 — VDD V
Reference Voltage
VREF
VDDQ/2 – 0.05
— VDDQ/2 + 0.05 V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter
Symbol
Min. Typ. Max. Unit
Junction Temperature
(Commercial Range Versions)
TJ
0 25 85 °C
Junction Temperature
(Industrial Range Versions)*
TJ
–40 25 100 °C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.00a 11/2011
11/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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