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PDF GS8342D37BD Data sheet ( Hoja de datos )

Número de pieza GS8342D37BD
Descripción 36Mb SigmaQuad-II+ Burst of 4 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8342D37BD Hoja de datos, Descripción, Manual

GS8342D07/10/19/37BD-450/400/350/333/300
165-Bump BGA
Commercial Temp
Industrial Temp
36Mb SigmaQuad-II+TM
Burst of 4 SRAM
450 MHz–300 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• 2.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (BW),
and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuadFamily Overview
The GS8342D07/10/19/37BD are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342D07/10/19/37BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342D07/10/19/37BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 4M x 8 has a 1M
addressable index).
tKHKH
tKHQV
-450
2.22 ns
0.45 ns
Parameter Synopsis
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
Rev: 1.02 6/2012
1/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS8342D37BD pdf
GS8342D07/10/19/37BD-450/400/350/333/300
1M x 36 SigmaQuad-II+ SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
NC/SA NC/SA
(288Mb ) (72Mb)
W
BW2
K
BW1
R
SA
NC/SA
(144Mb)
CQ
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 Q8
C D27 Q28 D19 VSS SA NC SA VSS D16 Q7 D8
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30 Q21 D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30 D22 Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
D1
P
Q35 D35 Q26
SA
SA QVLD SA
SA
Q9
D0
Q0
R
TDO TCK
SA
SA
SA ODT SA
SA
SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
3. BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
4. Pins A2, A3, and A10 are the expansion addresses.
Rev: 1.02 6/2012
5/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS8342D37BD arduino
GS8342D07/10/19/37BD-450/400/350/333/300
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1
11
01
10
00
D0–D3
Don’t Care
Data In
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.02 6/2012
11/29
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

11 Page







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