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PDF GS8342DT06BGD Data sheet ( Hoja de datos )

Número de pieza GS8342DT06BGD
Descripción 36Mb SigmaQuad-II+ Burst of 4 SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8342DT06BGD Hoja de datos, Descripción, Manual

165-Bump BGA
Commercial Temp
Industrial Temp
GS8342DT06/11/20/38BD-550/500/450/400/350
36Mb SigmaQuad-II+TM
Burst of 4 SRAM
550 MHz–350 MHz
1.8 V VDD
1.8 V or 1.5 V I/O
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) intputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaQuad-IIFamily Overview
The GS8342DT06/11/20/38BD are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GS8342DT06/11/20/38BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8342DT06/11/20/38BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 4M x 8 has a 1M
addressable index).
tKHKH
tKHQV
-550
1.81 ns
0.45 ns
Parameter Synopsis
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
-350
2.86 ns
0.45 ns
Rev: 1.01a 11/2012
1/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

1 page




GS8342DT06BGD pdf
GS8342DT06/11/20/38BD-550/500/450/400/350
4M x 8 SigmaQuad-II SRAM—Top View
123456789
A
CQ
NC/SA
(72Mb)
SA
W
NW1
K
NC/SA
(144Mb)
R
SA
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
NW0 SA
NC
C NC NC NC VSS SA NC SA VSS NC
D NC D4 NC VSS VSS VSS VSS VSS NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS VDDQ NC
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
G
NC D5
Q5
VDDQ
VDD
VSS
VDD VDDQ NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS VDDQ
NC
M NC NC NC VSS VSS VSS VSS VSS NC
N NC D7 NC VSS SA SA SA VSS NC
P NC NC Q7 SA SA QVLD SA SA NC
R
TDO TCK
SA
SA
SA ODT SA
SA
SA
11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch
Notes:
1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.
2. Pins A2, A7, and B5 are the expansion addresses.
10
SA
NC
NC
NC
D2
NC
NC
VREF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
Rev: 1.01a 11/2012
5/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

5 Page





GS8342DT06BGD arduino
GS8342DT06/11/20/38BD-550/500/450/400/350
Nybble Write Clock Truth Table
NW NW NW NW
Current Operation
DDDD
K
(tn+1)
T
K
(tn+1½)
T
K
(tn+2)
T
K
(tn+2½)
T
K
(tn)
Write
Dx stored if NWn = 0 in all four data transfers
K
(tn+1)
D0
K
(tn+1½)
D2
K
(tn+2)
D3
K
(tn+2½)
D4
T
F
F
F
Write
Dx stored if NWn = 0 in 1st data transfer only
D0
X
X
X
F
T
F
F
Write
Dx stored if NWn = 0 in 2nd data transfer only
X
D1
X
X
F
F
T
F
Write
Dx stored if NWn = 0 in 3rd data transfer only
X
X D2 X
F
F
F
T
Write
Dx stored if NWn = 0 in 4th data transfer only
X
X
X D3
F
F
F
F
Write Abort
No Dx stored in any of the four data transfers
X
X
X
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more NWn = 0, then NW = “T”, else NW = “F”.
x8 Nybble Write Enable (NWn) Truth Table
NW0 NW1
11
01
10
00
D0–D3
Don’t Care
Data In
Don’t Care
Data In
D4–D7
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.01a 11/2012
11/30
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

11 Page







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