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PDF GS82583EQ36GK Data sheet ( Hoja de datos )
| Número de pieza | GS82583EQ36GK | |
| Descripción | 288Mb SigmaQuad-IIIe Burst of 2 SRAM | |
| Fabricantes | GSI Technology | |
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GS82583EQ18/36GK-500/450/400
260-Pin BGA
Commercial Temp
Industrial Temp
288Mb SigmaQuad-IIIe™
Burst of 2 SRAM
Up to 500 MHz
1.3V VDD
1.2V, 1.3V, or 1.5V VDDQ
Features
• 8Mb x 36 and 16Mb x 18 organizations available
• 500 MHz maximum operating frequency
• 1.0 BT/s peak transaction rate (in billions per second)
• 72 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed DDR Address Bus
• Two operations - Read and Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
• 1.3V nominal core voltage
• 1.2V, 1.3V, or 1.5V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IIIe™ Family Overview
SigmaQuad-IIIe SRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
SRAMs. Although very similar to GSI's second generation of
networking SRAMs (the SigmaQuad-II/SigmaDDR-II family),
these third generation devices offer several new features that
help enable significantly higher performance.
Clocking and Addressing Schemes
The GS82583EQ18/36GK SigmaQuad-IIIe SRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B2
SRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 SRAM is always one address pin
less than the advertised index depth (e.g. the 16M x 18 has 8M
addressable index).
Speed Grade
-500
-450
-400
Parameter Synopsis
Max Operating Frequency
500 MHz
450 MHz
400 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.25V to 1.35V
1.25V to 1.35V
1.25V to 1.35V
Rev: 1.05 8/2016
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
1 page  
GS82583EQ18/36GK-500/450/400
Symbol
MVQ
VDD
VDDQ
VREF
VSS
TCK
TMS
TDI
TDO
MCH
MCL
NC
NUI
NUO
Description
I/O Voltage Select — Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V or 1.3V nominal VDDQ.
MVQ = 1: Configure for 1.5V nominal VDDQ.
Core Power Supply
I/O Power Supply
Input Reference Voltage — Input buffer reference voltage.
Ground
JTAG Clock — Weakly pulled Low internally.
JTAG Mode Select — Weakly pulled High internally.
JTAG Data Input — Weakly pulled High internally.
JTAG Data Output
Must Connect High — May be tied to VDDQ directly or via a 1k resistor.
Must Connect Low — May be tied to VSS directly or via a 1k resistor.
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Output — There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
Type
Input
—
—
—
—
Input
Input
Input
Output
Input
Input
—
Input
Output
Rev: 1.05 8/2016
5/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
5 Page 
GS82583EQ18/36GK-500/450/400
I/O Capacitance
Parameter
Input Capacitance
Output Capacitance
Notes:
1. VIN = VDDQ/2.
2. VOUT = VDDQ/2.
3. TA = 25C, f = 1 MHz.
Symbol
CIN
COUT
Min
—
—
Input Electrical Characteristics - 1.2V or 1.3V I/O (MVQ = 0)
Parameter
Symbol
Min
Typ
DC Input Reference Voltage
VREFdc
0.48 * VDDQ
0.50 * VDDQ
DC Input High Voltage (HS)
VIH1dc
VREF + 0.08
0.80 * VDDQ
DC Input Low Voltage (HS)
VIL1dc
-0.15
0.20 * VDDQ
DC Input High Voltage (LS)
VIH2dc
0.75 * VDDQ
VDDQ
DC Input Low Voltage (LS)
VIL2dc
-0.15
0
AC Input Reference Voltage
VREFac
0.47 * VDDQ
0.50 * VDDQ
AC Input High Voltage (HS)
VIH1ac
VREF + 0.15
0.80 * VDDQ
AC Input Low Voltage (HS)
VIL1ac
-0.25
0.20 * VDDQ
AC Input High Voltage (LS)
VIH2ac
VDDQ - 0.2
VDDQ
AC Input Low Voltage (LS)
VIL2ac
-0.25
0
Notes:
1. “Typ” parameter applies when Controller ROUTH = 40 and SRAM RINH = RINL = 120.
2. “Typ” parameter applies when Controller ROUTL = 40 and SRAM RINH = RINL = 120.
3. VREFac is equal to VREFdc plus noise.
4. VIH max and VIL min apply for pulse widths less than one-quarter of the cycle time.
5. Input rise and fall times must be a minimum of 1V/ns, and within 10% of each other.
6. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W.
7. Parameters apply to Low Speed Inputs: RST, DLL, MZT, PZT, MVQ.
Max Units Notes
5.0 pF 1, 3
5.5 pF 2, 3
Max
0.52 * VDDQ
VDDQ + 0.15
VREF - 0.08
VDDQ + 0.15
0.25 * VDDQ
0.53 * VDDQ
VDDQ + 0.25
VREF - 0.15
VDDQ + 0.25
0.2
Units
V
V
V
V
V
V
V
V
V
V
Notes
—
1, 6
2, 6
7
7
3
1, 4~6
2, 4~6
4, 7
4, 7
Rev: 1.05 8/2016
11/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology
11 Page | ||
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