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PDF GS8180QV36BD Data sheet ( Hoja de datos )

Número de pieza GS8180QV36BD
Descripción 18Mb Burst of 2 SigmaQuad SRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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GS8180QV18/36BD-200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb Burst of 2
SigmaQuad SRAM
200 MHz–167 MHz
2.5 V VDD
1.8 V or 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual DoubleData Rate interface
• Byte Write controls sampled at data-in time
• Burst of 2 Read and Write
• 2.5 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
• RoHS-compliant 165-bump, 13 mm x 15 mm, 1 mm bump
pitch BGA package
SigmaRAMFamily Overview
GS8180QV18/36B are built in compliance with the
SigmaQuad SRAM pinout standard for Separate I/O
synchronous SRAMs. They are18,874,368-bit (18Mb)
SRAMs. These are the first in a family of wide, very low
voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance
networking systems.
family of SigmaRAMs, the SigmaQuad family of SRAMs
allows a user to implement the interface protocol best suited to
the task at hand.
Clocking and Addressing Schemes
A Burst of 2 SigmaQuad SRAM is a synchronous device. It
employs two input register clock inputs, K and K. K and K are
independent single-ended clock inputs, not differential inputs
to a single differential clock input buffer. The device also
allows the user to manipulate the output register clock inputs
quasi independently with the C and C clock inputs. C and C are
also independent single-ended clock inputs, not differential
inputs. If the C clocks are tied high, the K clocks are routed
internally to fire the output registers instead.
Each internal read and write operation in a SigmaQuad-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed. Therefore the address field of a
SigmaQuad-II B2 RAM is always one address pin less than the
advertised index depth (e.g., the 2M x 8 has a 1M addressable
index).
SigmaQuad SRAMs are offered in a number of configurations.
Some emulate and enhance other synchronous separate I/O
SRAMs. A higher performance SDR (Single Data Rate) Burst
of 2 version is also offered. The logical differences between
the protocols employed by these RAMs hinge mainly on
various combinations of address bursting, output data
registering, and write cueing. Along with the Common I/O
Parameter Synopsis*
tKHKH
tKHQV
-200
5.0 ns
2.3 ns
-167
6.0 ns
2.5 ns
Rev: 1.02b 11/2011
1/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

1 page




GS8180QV36BD pdf
GS8180QV18/36BD-200/167
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
A SigmaQuad SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate
I/O SRAM that shares a common address between its two ports to keep both ports running all the time, the RAM must implement
some sort of burst transfer protocol. The burst must be at least long enough to cover the time the opposite port is receiving
instructions on what to do next. The rate at which a RAM can accept a new random address is the most fundamental performance
metric for the RAM. Each of the three SigmaQuad SRAMs support similar address rates because random address rate is
determined by the internal performance of the RAM and they are all based on the same internal circuits. Differences between the
truth tables of the different SigmaQuad SRAMs, or any other Separate I/O SRAMs, follow from differences in how the RAM’s
interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The
user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at
hand.
Burst of 2 SigmaQuad SRAM DDR Read
The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R,
begins a read cycle. Data can be clocked out one cycle later and again one half cycle after that. A high on the Read Enable-bar pin,
R, begins a read port deselect cycle.
Burst of 2 Double Data Rate SigmaQuad SRAM Read First
Read A
NOP
Write B
Read C Write D
Read E Write F
Read G Write H
NOP
K
K
Address
R
W
BWx
D
C
C
Q
A
BC
DE
FG
H
B B+1 D D+1 F F+1 H H+1
B B+1 D D+1 F F+1 H H+1
A A+1
C C+1 E E+1 G
Rev: 1.02b 11/2011
5/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

5 Page





GS8180QV36BD arduino
GS8180QV18/36BD-200/167
Separate I/O Burst of 2 SigmaQuad SRAM Read Truth Table
AR
Output Next State
KK
(tn) (tn)
K
(tn)
X1
Deselect
V0
Read
Notes:
1. X = Don’t Care, 1 = High, 0 = Low, V = Valid.
2. R is evaluated on the rising edge of K.
3. Q0 and Q1 are the first and second data output transfers in a read.
Separate I/O Burst of 2 SigmaQuad SRAM Write Truth Table
A W BWn BWn
Input Next State
K
(tn + ½)
K
(tn)
KK
(tn) (tn + ½)
K ↑, K
(tn), (tn + ½)
V000
Write Byte Dx0, Write Byte Dx1
V001
Write Byte Dx0, Write Abort Byte Dx1
V010
Write Abort Byte Dx0, Write Byte Dx1
X 0 1 1 Write Abort Byte Dx0, Write Abort Byte Dx1
X1XX
Deselect
Notes:
1. X = Don’t Care, H = High, L = Low, V = Valid.
2. W is evaluated on the rising edge of K.
3. D0 and D1 are the first and second data input transfers in a write.
4. BWn represents any of the Byte Write Enable inputs (BW0, BW1, etc.).
x18 Byte Write Enable (BWn) Truth Table
BW0
1
0
1
0
BW1
1
1
0
0
D0–D8
Don’t Care
Data In
Don’t Care
Data In
Q
K
(tn+1)
Hi-Z
Q0
Q
K
(tn+1½)
Hi-Z
Q1
DD
KK
(tn) (tn + ½)
D0 D1
D0 X
X D1
XX
XX
D9–D17
Don’t Care
Don’t Care
Data In
Data In
Rev: 1.02b 11/2011
11/28
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

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