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PDF GS81313LQ18GK Data sheet ( Hoja de datos )

Número de pieza GS81313LQ18GK
Descripción 144Mb SigmaQuad-IIIe Burst of 2 ECCRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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GS81313LQ18/36GK-800/714/600
260-Pin BGA
Com & Ind Temp
HSTL I/O
144Mb SigmaQuad-IIIe™
Burst of 2 ECCRAM™
Up to 800 MHz
1.25V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• 800 MHz maximum operating frequency
• 1.6 BT/s peak transaction rate (in billions per second)
• 115 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed DDR Address Bus
• Two operations - Read and Write - per clock cycle
• Burst of 2 Read and Write operations
• 3 cycle Read Latency
• On-chip ECC with virtually zero SER
• 1.25V ~ 1.3V core voltage
• 1.2V ~ 1.3V HSTL I/O interface
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IIIeFamily Overview
SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81313LQ18/36GK SigmaQuad-IIIe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 8M x 18 has
4M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-800
-714
-600
Parameter Synopsis
Max Operating Frequency
800 MHz
714 MHz
600 MHz
Read Latency
3 cycles
3 cycles
3 cycles
VDD
1.2V to 1.35V
1.2V to 1.35V
1.2V to 1.35V
Rev: 1.13 7/2016
1/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

1 page




GS81313LQ18GK pdf
GS81313LQ18/36GK-800/714/600
Symbol
PZT[1:0]
VDD
VDDQ
VREF
VSS
TCK
TMS
TDI
TDO
MCH
MCL
NC
NUI
NUO
Description
ODT Configuration Select — Set the ODT state for various combinations of input groups when MZT[1:0] =
01 or 10. Must be tied High or Low.
PZT[1:0] = 00: enables ODT on write data only.
PZT[1:0] = 01: enables ODT on write data and input clocks.
PZT[1:0] = 10: enables ODT on write data, address, and control.
PZT[1:0] = 11: enables ODT on write data, input clocks, address, and control.
Core Power Supply
I/O Power Supply
Input Reference Voltage — Input buffer reference voltage.
Ground
JTAG Clock — Weakly pulled Low internally.
JTAG Mode Select — Weakly pulled High internally.
JTAG Data Input — Weakly pulled High internally.
JTAG Data Output
Must Connect High — May be tied to VDDQ directly or via a 1kresistor.
Must Connect Low — May be tied to VSS directly or via a 1kresistor.
No Connect — There is no internal chip connection to these pins. They may be left unconnected, or tied/
driven High or Low.
Not Used Input — There is an internal chip connection to these input pins, but they are unused by the
device. They are pulled Low internally. They may be left unconnected or tied/driven Low. They should not be
tied/driven High.
Not Used Output — There is an internal chip connection to these output pins, but they are unused by the
device. The drivers are tri-stated internally. They should be left unconnected.
Type
Input
Input
Input
Input
Output
Input
Input
Input
Output
Rev: 1.13 7/2016
5/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

5 Page





GS81313LQ18GK arduino
GS81313LQ18/36GK-800/714/600
Absolute Maximum Ratings
Parameter
Symbol
Rating
Units Notes
Core Supply Voltage
VDD
-0.3 to +1.4
V
I/O Supply Voltage
VDDQ
-0.3 to VDD
V
Input Voltage (HS)
VIN1 -0.3 to VDDQ + 0.3
V2
VIN2 VDDQ - 1.5 to +1.7
Input Voltage (LS)
VIN3
-0.3 to VDDQ + 0.3
V3
Junction Temperature
TJ
0 to 125
C
Storage Temperature
TSTG
-55 to 125
C
Notes:
1. Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recom-
mended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions for an extended period of time
may affect reliability of this component.
2. Parameters apply to High Speed Inputs: CK, CK, KD, KD, SA, D, R, W. VIN1 and VIN2 must both be met.
3. Parameters apply to Low Speed Inputs: RST, PLL, MZT, PZT.
Recommended Operating Conditions
Parameter
Symbol Min Typ Max
Core Supply Voltage
VDD 1.2 1.25
I/O Supply Voltage
VDDQ 1.15 1.2
Commercial Junction Temperature
TJC 0 —
Industrial Junction Temperature
TJI -40 —
Note: For reliability purposes, power supplies must power up simultaneously, or in the following sequence:
VSS, VDD, VDDQ, VREF, and Inputs.
Power supplies must power down simultaneously, or in the reverse sequence.
1.35
VDD
85
100
Units
V
V
C
C
Notes
Thermal Impedances
Package
JA (C°/W)
JA (C°/W)
JA (C°/W)
Airflow = 0 m/s Airflow = 1 m/s Airflow = 2 m/s
FBGA
13.67
10.28
9.31
JB (C°/W)
3.08
JC (C°/W)
0.13
Rev: 1.13 7/2016
11/26
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2014, GSI Technology

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